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* [InstCombine] Inefficient pattern for high-bits checking (PR38708)Roman Lebedev2018-09-122-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: It is sometimes important to check that some newly-computed value is non-negative and only `n` bits wide (where `n` is a variable.) There are **many** ways to check that: https://godbolt.org/z/o4RB8D The last variant seems best? (I'm sure there are some other variations i haven't thought of..) Let's handle the second variant first, since it is much simpler. https://rise4fun.com/Alive/LYjY https://bugs.llvm.org/show_bug.cgi?id=38708 Reviewers: spatel, craig.topper, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51985 llvm-svn: 342067
* [objcopy] make objcopy follow program header standardsJulie Hockett2018-09-124-5/+21
| | | | | | | | | | | | | | | | | | Submitted on behalf of Armando Montanez (amontanez@google.com). Objects with unused program headers copied by objcopy would always have nonzero values for program header offset and program header entry size. While technically valid, this atypical behavior triggers warnings in some tools. This change sets the two fields to zero when the program header is unused, better fitting the general expectations for unused program header data. Section headers behaved somewhat similarly (though only with the entry size), and are fixed in this revision as well. Differential Revision: https://reviews.llvm.org/D51961 llvm-svn: 342065
* [WebAssembly] SIMD comparisonsThomas Lively2018-09-121-0/+644
| | | | | | | | | | | | | | | | Summary: Match the ordering semantics of non-vector comparisons. For floating point comparisons that do not correspond to instructions, the tests check that some vector comparison instruction was emitted but do not care about the full implementation. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51765 llvm-svn: 342064
* [ARM] Tighten f64<->f16 conversion requirementsDiogo N. Sampaio2018-09-122-0/+29
| | | | | | | | | | | | | | Fix missing Requires fields. Patch by Bernard Ogden (bogden) Reviewers: SjoerdMeijer, javed.absar, t.p.northover Reviewed By: t.p.northover Differential Revision: https://reviews.llvm.org/D51631 llvm-svn: 342061
* [X86] Remove isel patterns for ADCX instructionCraig Topper2018-09-125-215/+106
| | | | | | | | | | | | There's no advantage to this instruction unless you need to avoid touching other flag bits. It's encoding is longer, it can't fold an immediate, it doesn't write all the flags. I don't think gcc will generate this instruction either. Fixes PR38852. Differential Revision: https://reviews.llvm.org/D51754 llvm-svn: 342059
* Reverting r342048, which caused UBSan failures in dsymutil.Wolfgang Pieb2018-09-126-62/+29
| | | | llvm-svn: 342056
* [NFC][InstCombine] R38708 - inefficient pattern for high-bits checking.Roman Lebedev2018-09-122-0/+276
| | | | | | | | | | The simplest pattern for now: https://rise4fun.com/Alive/LYjY https://godbolt.org/z/o4RB8D https://bugs.llvm.org/show_bug.cgi?id=38708 llvm-svn: 342054
* [AArch64] Implement aarch64_vector_pcs codegen support.Sander de Smalen2018-09-121-0/+253
| | | | | | | | | | | | | | This patch adds codegen support for the saving/restoring V8-V23 for functions specified with the aarch64_vector_pcs calling convention attribute, as added in patch D51477. Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar, MatzeB Reviewed By: thegameg Differential Revision: https://reviews.llvm.org/D51479 llvm-svn: 342049
* [DWARF] Refactoring range list dumping to fold DWARF v4 functionality into ↵Wolfgang Pieb2018-09-126-29/+62
| | | | | | | | | | | | | v5 handling Eliminating some duplication of rangelist dumping code at the expense of some version-dependent code in dump and extract routines. Reviewer: dblaikie, JDevlieghere, vleschuk Differential revision: https://reviews.llvm.org/D51081 llvm-svn: 342048
* [CGP] Ensure splitgep gives deterministic outputDavid Green2018-09-121-0/+40
| | | | | | | | | | | | | | The output of splitLargeGEPOffsets does not appear to be deterministic because of the way that we iterate over a DenseMap. I've changed it to a MapVector for consistent output. The test here isn't particularly great, only showing a consmetic difference in output. The original reproducer is much larger but show a diffierence in instruction ordering, leading to different codegen. Differential Revision: https://reviews.llvm.org/D51851 llvm-svn: 342043
* [SimplifyCFG] Put an alignment on generated switch tablesDavid Green2018-09-121-6/+51
| | | | | | | | | | Previously the alignment on the newly created switch table data was not set, meaning that DataLayout::getPreferredAlignment was free to overalign it to 16 bytes. This causes unnecessary code bloat. Differential Revision: https://reviews.llvm.org/D51800 llvm-svn: 342039
* [ARM] Exchange MAC operands in ARMParallelDSPSam Parker2018-09-123-0/+737
| | | | | | | | | | | | | | | | SMLAD and SMLALD instructions also come in the form of SMLADX and SMLALDX which perform an exchange on their second operand. To support this, more of the loads in the MAC candidates are compared for sequential access and a boolean value has been added to BinOpChain. AddMACCandiate has been refactored into a small pattern matching state machine to reduce the amount of duplicated code, but also to enable the matching to be more flexible. CreateParallelMACPairs now iterates through all the candidates to find parallel ones. Differential Revision: https://reviews.llvm.org/D51424 llvm-svn: 342033
* [ARM] Allow bitcasts in ARMCodeGenPrepareSam Parker2018-09-121-0/+44
| | | | | | | | Allow bitcasts in the use-def chains, treating them as sources. Differential Revision: https://reviews.llvm.org/D50758 llvm-svn: 342032
* [AArch64] Add parsing of aarch64_vector_pcs attribute.Sander de Smalen2018-09-121-0/+11
| | | | | | | | | | | | | | | | | | | This patch adds parsing support for the 'aarch64_vector_pcs' calling convention attribute to calls and function declarations. More information describing the vector ABI and procedure call standard can be found here: https://developer.arm.com/products/software-development-tools/\ hpc/arm-compiler-for-hpc/vector-function-abi Reviewers: t.p.northover, rnk, rengolin, javed.absar, thegameg, SjoerdMeijer Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D51477 llvm-svn: 342030
* [LV] Move InterleaveGroup and InterleavedAccessInfo to VectorUtils.h (NFC)Florian Hahn2018-09-121-1/+1
| | | | | | | | | | | | | Move the 2 classes out of LoopVectorize.cpp to make it easier to re-use them for VPlan outside LoopVectorize.cpp Reviewers: Ayal, mssimpso, rengolin, dcaballe, mkuper, hsaito, hfinkel, xbolva00 Reviewed By: rengolin, xbolva00 Differential Revision: https://reviews.llvm.org/D49488 llvm-svn: 342027
* Revert "AMDGPU: Move isa version and EF_AMDGPU_MACH_* determination into ↵Ilya Biryukov2018-09-122-9/+1
| | | | | | | | | | | TargetParser." This reverts commit r341982. The change introduced a layering violation. Reverting to unbreak our integrate. llvm-svn: 342023
* [X86] Teach X86SelectionDAGInfo::EmitTargetCodeForMemcpy about GNUX32Craig Topper2018-09-121-0/+47
| | | | | | | | | | | | | | | | | Summary: In GNUX23, is64BitMode returns true, but pointers are 32-bits. So we shouldn't copy pointer values into RSI/RDI since the widths don't match. Fixes PR38865 despite what the title says. I think the llvm_unreachable in the copyPhysReg code tricked the optimizer and made the fatal error trigger. Reviewers: rnk, efriedma, MatzeB, echristo Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D51893 llvm-svn: 342015
* [MachineOutliner] Add codegen size remarks to the MachineOutlinerJessica Paquette2018-09-111-0/+81
| | | | | | | | | | | | | | | | Since the outliner is a module pass, it doesn't get codegen size remarks like the other codegen passes do. This adds size remarks *to* the outliner. This is kind of a workaround, so it's peppered with FIXMEs; size remarks really ought to not ever be handled by the pass itself. However, since the outliner is the only "MachineModulePass", this works for now. Since the entire purpose of the MachineOutliner is to produce code size savings, it really ought to be included in codgen size remarks. If we ever go ahead and make a MachineModulePass (say, something similar to MachineFunctionPass), then all of this ought to be moved there. llvm-svn: 342009
* [InstCombine] add folds for unsigned-overflow comparesSanjay Patel2018-09-111-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Name: op_ugt_sum %a = add i8 %x, %y %r = icmp ugt i8 %x, %a => %notx = xor i8 %x, -1 %r = icmp ugt i8 %y, %notx Name: sum_ult_op %a = add i8 %x, %y %r = icmp ult i8 %a, %x => %notx = xor i8 %x, -1 %r = icmp ugt i8 %y, %notx https://rise4fun.com/Alive/ZRxI AFAICT, this doesn't interfere with any add-saturation patterns because those have >1 use for the 'add'. But this should be better for IR analysis and codegen in the basic cases. This is another fold inspired by PR14613: https://bugs.llvm.org/show_bug.cgi?id=14613 llvm-svn: 342004
* Revert "[GVNHoist] Re-enable GVNHoist by default"Alexandros Lamprineas2018-09-115-26/+22
| | | | | | | | | | | | | | This reverts rL341954. The builder `sanitizer-x86_64-linux-bootstrap-ubsan` has been failing with timeouts at stage2 clang/ubsan: [3065/3073] Linking CXX executable bin/lld command timed out: 1200 seconds without output running python ../sanitizer_buildbot/sanitizers/buildbot_selector.py, attempting to kill llvm-svn: 342001
* [codeview] Decode and dump FP regs from S_FRAMEPROC recordsReid Kleckner2018-09-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: There are two registers encoded in the S_FRAMEPROC flags: one for locals and one for parameters. The encoding is described by the ExpandEncodedBasePointerReg function in cvinfo.h. Two bits are used to indicate one of four possible values: 0: no register - Used when there are no variables. 1: SP / standard - Variables are stored relative to the standard SP for the ISA. 2: FP - Variables are addressed relative to the ISA frame pointer, i.e. EBP on x86. If realignment is required, parameters use this. If a dynamic alloca is used, locals will be EBP relative. 3: Alternative - Variables are stored relative to some alternative third callee-saved register. This is required to address highly aligned locals when there are dynamic stack adjustments. In this case, both the incoming SP saved in the standard FP and the current SP are at some dynamic offset from the locals. LLVM uses ESI in this case, MSVC uses EBX. Most of the changes in this patch are to pass around the CPU so that we can decode these into real, named architectural registers. Subscribers: hiraditya Differential Revision: https://reviews.llvm.org/D51894 llvm-svn: 341999
* [InstCombine] add folds for icmp with xor mask constantSanjay Patel2018-09-111-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are the folds in Alive; Name: xor_ult Pre: isPowerOf2(-C1) %xor = xor i8 %x, C1 %r = icmp ult i8 %xor, C1 => %r = icmp ugt i8 %x, ~C1 Name: xor_ugt Pre: isPowerOf2(C1+1) %xor = xor i8 %x, C1 %r = icmp ugt i8 %xor, C1 => %r = icmp ugt i8 %x, C1 https://rise4fun.com/Alive/Vty The ugt case in its simplest form was already handled by DemandedBits, but that's not ideal as shown in the multi-use test. I'm not sure if these are all of the symmetrical folds, but I adjusted the existing code for one of the folds to try to show the similarities. There's no obvious connection, but this is another preliminary step for PR14613... https://bugs.llvm.org/show_bug.cgi?id=14613 llvm-svn: 341997
* add IR flags to MIMichael Berg2018-09-111-5/+6
| | | | | | | | | | | | | | Summary: Initial support for nsw, nuw and exact flags in MI Reviewers: spatel, hfinkel, wristow Reviewed By: spatel Subscribers: nlopes Differential Revision: https://reviews.llvm.org/D51738 llvm-svn: 341996
* Revert "[SanitizerCoverage] Create comdat for global arrays."Matt Morehouse2018-09-115-7/+7
| | | | | | | This reverts r341987 since it will cause trouble when there's a module ID collision. llvm-svn: 341995
* [InstCombine] add tests for icmp with xor; NFCSanjay Patel2018-09-111-0/+47
| | | | llvm-svn: 341993
* [SanitizerCoverage] Create comdat for global arrays.Matt Morehouse2018-09-115-7/+7
| | | | | | | | | | | | | | | | | Summary: Place global arrays in comdat sections with their associated functions. This makes sure they are stripped along with the functions they reference, even on the BFD linker. Reviewers: eugenis Reviewed By: eugenis Subscribers: eraman, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51902 llvm-svn: 341987
* Update MemorySSA in LoopUnswitch.Alina Sbirlea2018-09-1135-2/+36
| | | | | | | | | | | | Summary: Update MemorySSA in old LoopUnswitch pass. Actual dependency and update is disabled by default. Subscribers: sanjoy, jlebar, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D45301 llvm-svn: 341984
* AMDGPU: Move isa version and EF_AMDGPU_MACH_* determinationKonstantin Zhuravlyov2018-09-112-1/+9
| | | | | | | | | | | | | | into TargetParser. Also switch away from target features to CPU string when determining isa version. This fixes an issue when we output wrong isa version in the object code when features of a particular CPU are altered (i.e. gfx902 w/o xnack used to result in gfx900). Differential Revision: https://reviews.llvm.org/D51890 llvm-svn: 341982
* [InstCombine] enhance vector demanded elements to look at a vector select ↵Sanjay Patel2018-09-111-5/+5
| | | | | | | | | | | | | | | condition operand I noticed that we were not back-propagating undef lanes to shuffle masks when we have a shuffle that reduces the vector width. This is part of investigating/solving PR38691: https://bugs.llvm.org/show_bug.cgi?id=38691 The DAG equivalent was proposed with: D51696 Differential Revision: https://reviews.llvm.org/D51433 llvm-svn: 341981
* [InstCombine] add tests for add-with-overflow compares; NFCSanjay Patel2018-09-111-21/+116
| | | | llvm-svn: 341979
* [X86] Prefer unpckhpd over movhlps in isel for fake unary casesCraig Topper2018-09-1121-250/+250
| | | | | | | | | | | | In r337348, I changed lowering to prefer X86ISD::UNPCKL/UNPCKH opcodes over MOVLHPS/MOVHLPS for v2f64 {0,0} and {1,1} shuffles when we have SSE2. This enabled the removal of a bunch of weirdly bitcasted isel patterns in r337349. To avoid changing the tests I placed a gross hack in isel to still emit movhlps instructions for fake unary unpckh nodes. A similar hack was not needed for unpckl and movlhps because we do execution domain switching for those. But unpckh and movhlps have swapped operand order. This patch removes the hack. This is a code size increase since unpckhpd requires a 0x66 prefix and movhlps does not. But if that's a big concern we should be using movhlps for all unpckhpd opcodes and let commuteInstruction turnit into unpckhpd when its an advantage. Differential Revision: https://reviews.llvm.org/D49499 llvm-svn: 341973
* [X86] Teach X86FastISel::X86SelectRet to use EAX for the sret pointer in GNUX32Craig Topper2018-09-111-0/+23
| | | | | | | | | | GNUX32 uses 32-bit pointers despite is64BitMode being true. So we should use EAX to return the value. Fixes ones of the failures from PR38865. Differential Revision: https://reviews.llvm.org/D51940 llvm-svn: 341972
* [InstCombine] Fix incorrect usage of getPrimitiveSizeInBits when we should ↵Craig Topper2018-09-111-1/+1
| | | | | | | | | | be using the element size for vectors For vectors, getPrimitiveSizeInBits returns the full vector width. This code should using the element size for vectors. This could be fixed by calling getScalarSizeInBits, but its even easier to just get it from the APInt we're checking. Differential Revision: https://reviews.llvm.org/D51938 llvm-svn: 341971
* [CallSiteSplitting] Add debug location to created PHI nodes.Florian Hahn2018-09-111-0/+85
| | | | | | | | | | | | | | | | | | | | | | There are 2 cases when we create PHI nodes: * For the result of the call that was duplicated in the split blocks. Those PHI nodes should have the debug location of the call. * For values produced before the call. Those instructions need to be duplicated in the split blocks and the PHI nodes should have the debug locations of those instructions. Fixes PR37962. Reviewers: junbuml, gbedwell, vsk Reviewed By: junbuml Tags: #debug-info Differential Revision: https://reviews.llvm.org/D51919 llvm-svn: 341970
* [GlobalISel] Lower dbg.declare into indirect DBG_VALUEJosh Stone2018-09-112-3/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: D31439 changed the semantics of dbg.declare to take the address of a variable as the first argument, making it indirect. It specifically updated FastISel for this change here: https://reviews.llvm.org/D31439#change-WVArzi177jPl GlobalISel needs to follow suit, or else it will be missing a level of indirection in the generated debuginfo. This problem was seen in a Rust debuginfo test on aarch64, since GlobalISel is used at -O0 for aarch64. https://github.com/rust-lang/rust/issues/49807 https://bugzilla.redhat.com/show_bug.cgi?id=1611597 https://bugzilla.redhat.com/show_bug.cgi?id=1625768 Reviewers: dblaikie, aprantl, t.p.northover, javed.absar, rnk Reviewed By: rnk Subscribers: #debug-info, rovka, kristof.beyls, JDevlieghere, llvm-commits, tstellar Differential Revision: https://reviews.llvm.org/D51749 llvm-svn: 341969
* Revert "[SanitizerCoverage] Create comdat for global arrays."Matt Morehouse2018-09-115-7/+7
| | | | | | This reverts r341951 due to bot breakage. llvm-svn: 341965
* [InstCombine] Support (mul (sext x), cst) --> (sext (mul x, cst')) and (mul ↵Craig Topper2018-09-111-14/+14
| | | | | | | | | | (zext x), cst) --> (zext (mul x, cst')) for vectors constants. Similar to D51236, but for mul instead of add. Differential Revision: https://reviews.llvm.org/D51900 llvm-svn: 341961
* [GVNHoist] Re-enable GVNHoist by defaultAlexandros Lamprineas2018-09-115-22/+26
| | | | | | | Rebase rL340922 since https://bugs.llvm.org/show_bug.cgi?id=38807 has been fixed by rL341947. llvm-svn: 341954
* [DagCombine][NFC] Some more tests fo for X % C == 0 (UREM case) transformRoman Lebedev2018-09-116-4/+1823
| | | | | | | | For https://reviews.llvm.org/D50222 Patch by: hermord (Dmytro Shynkevych)! llvm-svn: 341953
* [MIPS] Fix illegal type assert in single-float modeSimon Atanasyan2018-09-111-0/+52
| | | | | | | | | | | | An fp_to_sint node would be incorrectly lowered to a TruncIntFP node in single-float mode. This would trigger an "Unexpected illegal type!" assert. Patch by Dan Ravensloft. Differential revision: https://reviews.llvm.org/D51810 llvm-svn: 341952
* [SanitizerCoverage] Create comdat for global arrays.Matt Morehouse2018-09-115-7/+7
| | | | | | | | | | | | | | | | | Summary: Place global arrays in comdat sections with their associated functions. This makes sure they are stripped along with the functions they reference, even on the BFD linker. Reviewers: eugenis Reviewed By: eugenis Subscribers: eraman, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D51902 llvm-svn: 341951
* [MemorySSAUpdater] Avoid creating self-referencing MemoryDefsAlexandros Lamprineas2018-09-111-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for https://bugs.llvm.org/show_bug.cgi?id=38807, which occurred while compiling SemaTemplateInstantiate.cpp with clang and GVNHoist enabled. In the following example: 1=def(entry) / \ 2=def(1) 4=def(1) 3=def(2) 5=def(4) When removing the MemoryDef 2=def(1) from its basic block, and just before adding it to the end of the parent basic block, we first replace all its uses with the defining memory access: 3=def(2) -> 3=def(1) Then we call insertDef for adding 2=def(1) to the parent basic block, where we replace the uses of 1=def(entry) with 2=def(1). Doing so we create a self reference: 2=def(1) -> 2=def(2) (bad) 3=def(1) -> 3=def(2) (ok) 4=def(1) -> 4=def(2) (ok) Differential Revision: https://reviews.llvm.org/D51801 llvm-svn: 341947
* Make malformed-machos.test pass on my Mac.Nico Weber2018-09-111-1/+1
| | | | | | | For some reason, llvm-objdump defaults to -arch=i386 on this system while the test checks x86_64 output. Explicitly pass -arch=x86_64. llvm-svn: 341944
* [Hexagon] [Test] Remove undef and infinite loop from testRoman Lebedev2018-09-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The undef and the infinite loop at the end cause this test to be translated unpredictably. In particular, the checked-for `mpy` disappears under certain legal optimizations (e.g. the one in D50222). Since the use of these constructs is not relevant to the behavior tested, according to the header comment, this change, suggested by @kparzysz, eliminates them. Was initially committed in r341046, but was reverted. Patch by: hermord (Dmytro Shynkevych)! Reviewers: kparzysz Reviewed By: kparzysz Subscribers: lebedev.ri, llvm-commits, kparzysz Differential Revision: https://reviews.llvm.org/D50944 llvm-svn: 341943
* [ARM] Add smlald support in ARMParallelDSPSam Parker2018-09-113-0/+364
| | | | | | | | | Search from i64 reducing phis, as well as i32, to allow the generation of smlald instructions. Differential Revision: https://reviews.llvm.org/D51101 llvm-svn: 341941
* [AArch64] test codegen for unsigned saturated add; NFCSanjay Patel2018-09-111-0/+729
| | | | | | | This is identical to the tests added for x86 at rL341845. A semi-generic DAGCombine should improve things universally. llvm-svn: 341935
* [MIPS] ORC JIT supportPetar Jovanovic2018-09-111-1/+1
| | | | | | | | | | | | This patch adds support for ORC JIT for mips/mips64 architecture. In common code $static is changed to __ORCstatic because on MIPS architecture "$" is a reserved character. Patch by Luka Ercegovcevic Differential Revision: https://reviews.llvm.org/D49665 llvm-svn: 341934
* [AMDGPU] Preliminary patch for divergence driven instruction selection. ↵Alexander Timofeev2018-09-1148-467/+429
| | | | | | | | | Immediate selection predicate changed Differential revision: https://reviews.llvm.org/D51734 Reviewers: rampitec llvm-svn: 341928
* [FuncAttrs] Remove "access range attributes" for read-none functionsJohannes Doerfert2018-09-111-0/+32
| | | | | | | | | | The presence of readnone and an access range attribute (argmemonly, inaccessiblememonly, inaccessiblemem_or_argmemonly) is considered an error by the verifier. This seems strict but also not wrong. This patch makes sure function attribute detection will remove all access range attributes for readnone functions. llvm-svn: 341927
* [mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instructionSimon Atanasyan2018-09-111-4/+4
| | | | | | | | | | | | | | | | | | | | | MIPS ISAs start to support third operand for the `rdhwr` instruction starting from Revision 6. But LLVM generates assembler code with three-operands version of this instruction on any MIPS64 ISA. The third operand is always zero, so in case of direct code generation we get correct code. This patch fixes the bug by adding an instruction alias. The same alias already exists for 32-bit ISA. Ideally, we also need to reject three-operands version of the `rdhwr` instruction in an assembler code if ISA revision is less than 6. That is a task for a separate patch. This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861) Differential revision: https://reviews.llvm.org/D51773 llvm-svn: 341919
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