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* Re-commit: [mips] abs.[ds], and neg.[ds] should be allowed regardless of ↵Daniel Sanders2014-04-093-39/+53
| | | | | | | | | | | | | | | | | | | -enable-no-nans-fp-math Summary: They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies). nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008. Fixed the issue with the previous version of this patch (r205628). A pre-existing 'let Predicate =' statement was removing some predicates that were necessary for FP64 to behave correctly. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3274 llvm-svn: 205844
* YAMLIO: Encode ambiguous hex strings explicitlyDavid Majnemer2014-04-091-1/+1
| | | | | | | | | | YAMLIO would turn a BinaryRef into the string 0000000004000000. However, the leading zero causes parsers to interpret it as being an octal number instead of a hexadecimal one. Instead, escape such strings as needed. llvm-svn: 205839
* R600/SI: Match not instruction.Matt Arsenault2014-04-091-0/+18
| | | | llvm-svn: 205837
* ARM64: scalarize v1i64 mul operationTim Northover2014-04-091-0/+7
| | | | | | This is the second part of fixing PR19367. llvm-svn: 205836
* ARM64: add pattern for <1 x i64> custom not node.Tim Northover2014-04-091-0/+9
| | | | | | This should fix PR19367. llvm-svn: 205835
* WinCOFF: Emit common symbols as specified in the COFF specDavid Majnemer2014-04-082-4/+4
| | | | | | | | | | | | | | | | | | Summary: Local common symbols were properly inserted into the .bss section. However, putting external common symbols in the .bss section would give them a strong definition. Instead, encode them as undefined, external symbols who's symbol value is equivalent to their size. Reviewers: Bigcheese, rafael, rnk CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3324 llvm-svn: 205811
* in findGCD of multiply expr return the gcdSebastian Pop2014-04-081-0/+153
| | | | | | we used to return 1 instead of the gcd llvm-svn: 205800
* [Constant Hoisting][ARM64] Enable constant hoisting for ARM64.Juergen Ributzka2014-04-083-0/+49
| | | | | | | | This implements the target-hooks for ARM64 to enable constant hoisting. This fixes <rdar://problem/14774662> and <rdar://problem/16381500>. llvm-svn: 205791
* Fix the ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2014-04-081-1/+1
| | | | | | | | | | | | | | | size 16 double-spaced registers instruction printing. This: vld3.16 {d0[], d2[], d4[]}, [r4]! was being printed as: vld3.16 {d0[], d1[], d2[]}, [r4]! rdar://16531387 llvm-svn: 205779
* Add -pass-remarks flag to 'opt'.Diego Novillo2014-04-081-0/+33
| | | | | | | | | | | | | | | | | | | | | Summary: This adds support in 'opt' to filter pass remarks emitted by optimization passes. A new flag -pass-remarks specifies which passes should emit a diagnostic when LLVMContext::emitOptimizationRemark is invoked. This will allow the front end to simply pass along the regular expression from its own -Rpass flag when launching the backend. Depends on D3227. Reviewers: qcolombet CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D3291 llvm-svn: 205775
* X86MCAsmInfoGNUCOFF: Set PointerSize as 8 for targeting x64. It caused ↵NAKAMURA Takumi2014-04-082-6/+0
| | | | | | | DW_LNE_set_address was misemitted on x64. FIXME: I haven't investigate whether CalleeSaveStackSlotSize should be 8. llvm-svn: 205772
* ARM64: fix fmsub patterns which assumed accum operand was firstTim Northover2014-04-081-10/+10
| | | | | | | | | | Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
* AVX-512: Added fp_to_uint and uint_to_fp patterns.Elena Demikhovsky2014-04-081-0/+32
| | | | llvm-svn: 205754
* obj2yaml: Use the correct relocation type for different machine typesDavid Majnemer2014-04-073-2/+35
| | | | | | | | | | | | | The IO normalizer would essentially lump I386 and AMD64 relocations together. Relocation types with the same numeric value would then get mapped in appropriately. For example: IMAGE_REL_AMD64_ADDR64 and IMAGE_REL_I386_DIR16 both have a numeric value of one. We would see IMAGE_REL_I386_DIR16 in obj2yaml conversions of object files with a machine type of IMAGE_FILE_MACHINE_AMD64. llvm-svn: 205746
* Reverting commit r205628 due to mips64 issues.Reed Kotler2014-04-073-47/+39
| | | | llvm-svn: 205741
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-071-0/+26
| | | | llvm-svn: 205732
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-075-68/+100
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* Revert the last couple of patches here and go back to somethingEric Christopher2014-04-071-1/+3
| | | | | | that at least failed reliably. llvm-svn: 205711
* Handle vlas during inline cost computation if they'll be turnedEric Christopher2014-04-071-0/+38
| | | | | | | | | | | into a constant size alloca by inlining. Ran a run over the testsuite, no results out of the noise, fixes the testcase in the PR. PR19115. llvm-svn: 205710
* XFAIL this completely at the moment:Eric Christopher2014-04-071-0/+1
| | | | | | | | | cygwin has llvm-dwarfdump problems and isn't paying attention to the specific xfail there. s390x isn't matching for an unknown reason. llvm-svn: 205708
* Make test run on most platforms and only fail on cygwin/mingw whileEric Christopher2014-04-071-4/+1
| | | | | | it's being investigated for those. llvm-svn: 205704
* Quick fix: Triple::isOSMSVCRT() should be false for targeting cygwin.NAKAMURA Takumi2014-04-061-0/+23
| | | | | | | | It affected callee's stack pop in x86. It is one of devergences between cygwin and mingw since mingw-gcc-4.6. Added testcases to llvm/test/CodeGen/X86/win32_sret.ll for cygwin. llvm-svn: 205688
* DebugInfo: Support namespace aliases as DW_TAG_imported_declaration instead ↵David Blaikie2014-04-061-4/+4
| | | | | | | | | | | | | | | | of DW_TAG_imported_module I really should read the spec more often (and test GCC more often too). I just assumed that namespace aliases would be the same as using directives, except with a name. But apparently that's not how the DWARF standards suggests they be implemented. DWARF4 provides an example and other non-normative text suggesting that namespace aliases be implemented by named imported declarations intsead of named imported modules. So be it. llvm-svn: 205685
* AsmParser: add a warning for compatibility parsingSaleem Abdulrasool2014-04-051-0/+9
| | | | | | | | | This adds a warning when linker_private or linker_private_weak is provided and we handle it in a compatible manner. Suggested by Chris Lattner! llvm-svn: 205681
* ARM: consolidate MachO checks for ARM asm parserSaleem Abdulrasool2014-04-051-9/+14
| | | | | | | | | | | | | | | | | | | This consolidates the duplicated MachO checks in the directive parsing for various directives that are unsupported for Mach-O. The error message change is unimportant as this restores the behaviour to that prior to the addition of the new directive handling. Furthermore, use a more direct check for MachO targeting rather than an indirect feature check of the assembler. Also simplify the test execution command to avoid temporary files. Further more, perform the check in both object and assembly emission. Whether all non-applicable directives are handled is another question. .fnstart is marked as being unsupported, however, the complementary .fnend is not. The additional unwinding directives are also still honoured. This change does not change that, though, it would be good to validate and mark them as being unsupported if they are unsupported for the MachO emission. llvm-svn: 205678
* AsmParser: restore LLVM IR compatibility for linker_private{,_weak}Saleem Abdulrasool2014-04-051-0/+8
| | | | | | | | | | | This restores the linker_private and linker_private_weak lexemes to permit translation of the deprecated lexmes. The behaviour is identical to the bitcode handling: linker_private and linker_private_weak are handled as if private had been specified. This enables compatibility with IR generated by LLVM 3.4. Reported on IRC by ki9a! llvm-svn: 205675
* [PowerPC] Adjust load/store costs in PPCTTIHal Finkel2014-04-043-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | This provides more realistic costs for the insert/extractelement instructions (which are load/store pairs), accounts for the cheap unaligned Altivec load sequence, and for unaligned VSX load/stores. Bad news: MultiSource/Applications/sgefa/sgefa - 35% slowdown (this will require more investigation) SingleSource/Benchmarks/McGill/queens - 20% slowdown (we no longer vectorize this, but it was a constant store that was scalarized) MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2 - 2% slowdown Good news: SingleSource/Benchmarks/Shootout/ary3 - 54% speedup SingleSource/Benchmarks/Shootout-C++/ary - 40% speedup MultiSource/Benchmarks/Ptrdist/ks/ks - 35% speedup MultiSource/Benchmarks/FreeBench/neural/neural - 30% speedup MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt - 20% speedup Unfortunately, estimating the costs of the stack-based scalarization sequences is hard, and adjusting these costs is like a game of whac-a-mole :( I'll revisit this again after we have better codegen for vector extloads and truncstores and unaligned load/stores. llvm-svn: 205658
* Update the test to use FileCheck.Juergen Ributzka2014-04-041-2/+8
| | | | llvm-svn: 205647
* [mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.Kai Nacke2014-04-041-0/+20
| | | | | | | | | This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu. It is only for the assembler. Test case is included. Reviewed by: Daniel.Sanders@imgtec.com llvm-svn: 205631
* [PowerPC] Add a full condition code register to make the "cc" clobber workHal Finkel2014-04-041-0/+70
| | | | | | | | gcc inline asm supports specifying "cc" as a clobber of all condition registers. Add just enough modeling of the full register to make this work. Fixed PR19326. llvm-svn: 205630
* [mips] abs.[ds], and neg.[ds] should be allowed regardless of ↵Daniel Sanders2014-04-043-39/+47
| | | | | | | | | | | | | | | | | | | | | | -enable-no-nans-fp-math Summary: They behave in accordance with the Has2008 and ABS2008 configuration bits of the processor which are used to select between the 1985 and 2008 versions of IEEE 754. In 1985 mode, these instructions are arithmetic (i.e. they raise invalid operation exceptions when given NaN), in 2008 mode they are non-arithmetic (i.e. they are copies). nmadd.[ds], and nmsub.[ds] are still subject to -enable-no-nans-fp-math because the ISA spec does not explicitly state that they obey Has2008 and ABS2008. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3274 llvm-svn: 205628
* DAGLegalize: add last-ditch type-legalization for VSELECT.Tim Northover2014-04-041-0/+9
| | | | | | | | | | | | | When LLVM sees something like (v1iN (vselect v1i1, v1iN, v1iN)) it can decide that the result is OK (v1i64 is legal on AArch64, for example) but it still need scalarising because of that v1i1. There was no code to do this though. AArch64 and ARM64 have DAG combines to produce efficient code and prevent that occuring in *most* such situations, but there are edge cases that they miss. This adds a legalization to cope with that. llvm-svn: 205626
* ARM64: handle v1i1 types arising from setcc properly.Tim Northover2014-04-041-0/+65
| | | | | | | | | | | | | | | | | | | | There were several overlapping problems here, and this solution is closely inspired by the one adopted in AArch64 in r201381. Firstly, scalarisation of v1i1 setcc operations simply fails if the input types are legal. This is fixed in LegalizeVectorTypes.cpp this time, and allows AArch64 code to be simplified slightly. Second, vselect with such a setcc feeding into it ends up in ScalarizeVectorOperand, where it's not handled. I experimented with an implementation, but found that whatever DAG came out was rather horrific. I think Hao's DAG combine approach is a good one for quality, though there are edge cases it won't catch (to be fixed separately). Should fix PR19335. llvm-svn: 205625
* Fix for PR18921 (LDRD/STRD part)::Stepan Dyatkovskiy2014-04-044-0/+59
| | | | | | | | Removed "GNU Assembler extension (compatibility)" definitions from ARMInstrInfo.td Fixed ARMAsmParser::ParseInstruction GNU compatability branch, so it also works for thumb mode from now. Added new tests. llvm-svn: 205622
* Tweak unconditional-branch.ll passing on any hosts, while investigating ↵NAKAMURA Takumi2014-04-041-2/+6
| | | | | | | | | | | | | | | | | | x86_64-mingw32. Sorry for the breakage. For now, it will fail in two ways: 1. To fail for targeting x86_64-mingw32. <stdin>:131:8: note: possible intended match here 0x30830a0100000002 3 0 1 0 0 is_stmt 2. To fail not to find the target x86. llc: : error: unable to get target for 'x86_64-unknown-unknown', see --version and --triple. llvm-svn: 205621
* ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcastsTim Northover2014-04-041-0/+12
| | | | | | | | | | | | | | | | | | The previous patterns directly inserted FMOV or INS instructions into the DAG for scalar_to_vector & bitconvert patterns. This is horribly inefficient and can generated lots more GPR <-> FPR register traffic than necessary. It's much better to emit instructions the register allocator understands so it can coalesce the copies when appropriate. It led to at least one ISelLowering hack to avoid the problems, which was incorrect for v1i64 (FPR64 has no dsub). It can now be removed entirely. This should also fix PR19331. llvm-svn: 205616
* ARM64: add 128-bit MLA operations to the custom selection code.Tim Northover2014-04-041-0/+26
| | | | | | | | | | | Without this change, the llvm_unreachable kicked in. The code pattern being spotted is rather non-canonical for 128-bit MLAs, but it can happen and there's no point in generating sub-optimal code for it just because it looks odd. Should fix PR19332. llvm-svn: 205615
* Fixed register class in STRD instruction for Thumb2 mode.Stepan Dyatkovskiy2014-04-042-0/+16
| | | | llvm-svn: 205612
* [RegAllocGreedy][Last Chance Recoloring] Emit diagnostics when last chanceQuentin Colombet2014-04-041-0/+8
| | | | | | | | | | recoloring cut-offs are encountered and register allocation failed. This is related to PR18747 Patch by MAYUR PANDEY <mayur.p@samsung.com>. llvm-svn: 205601
* Revert r205599, the commit was not intended to have so many changesQuentin Colombet2014-04-041-8/+0
| | | | llvm-svn: 205600
* [RegAllocGreedy][Last Chance Recoloring] Emit diagnostics when last chanceQuentin Colombet2014-04-041-0/+8
| | | | | | | | | | recoloring cut-offs are hit. This is related to PR18747. Patch by MAYUR PANDEY <mayur.p@samsung.com> llvm-svn: 205599
* ARM: fix test case missed in previous roundupSaleem Abdulrasool2014-04-041-2/+2
| | | | | | This should hopefully bring the last MSVC buildbot back to green! llvm-svn: 205596
* Implement getRelocationAddress for MachO and ET_REL elf files.Rafael Espindola2014-04-033-0/+20
| | | | | | With that, fix the symbolizer to work with any ELF file. llvm-svn: 205588
* ARM: yet another round of ARM test clean upsSaleem Abdulrasool2014-04-03108-143/+190
| | | | llvm-svn: 205586
* Fix llvm-objdump crash.Rafael Espindola2014-04-031-3/+1
| | | | llvm-svn: 205581
* Optimize away unnecessary address casts.Eli Bendersky2014-04-032-2/+93
| | | | | | | | | Removes unnecessary casts from non-generic address spaces to the generic address space for certain code patterns. Patch by Jingyue Wu. llvm-svn: 205571
* [ARM64] Teach the ARM64DeadRegisterDefinition pass to respect implicit-defs.Lang Hames2014-04-031-0/+32
| | | | | | | | | | | | | When rematerializing through truncates, the coalescer may produce instructions with dead defs, but live implicit-defs of subregs: E.g. %X1<def,dead> = MOVi64imm 2, %W1<imp-def>; %X1:GPR64, %W1:GPR32 These instructions are live, and their definitions should not be rewritten. Fixes <rdar://problem/16492408> llvm-svn: 205565
* unconditional-branch.ll is broken for targeting x86_64-cygming. Add an ↵NAKAMURA Takumi2014-04-031-1/+2
| | | | | | explicit triple for now. llvm-svn: 205563
* R600: Correct opcode for BFE_INTTom Stellard2014-04-031-1/+2
| | | | | | | | | | | Acording to AMD documentation, the correct opcode for BFE_INT is 0x5, not 0x4 Fixes Arithm/Absdiff.Mat/3 OpenCV test Patch by: Bruno Jiménez llvm-svn: 205562
* R600/SI: Lower 64-bit immediates using REG_SEQUENCETom Stellard2014-04-032-4/+5
| | | | llvm-svn: 205561
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