diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2014-04-03 20:19:27 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-04-03 20:19:27 +0000 |
| commit | 7ed0b5235a2d97bf8d81e36401478ce056152152 (patch) | |
| tree | b2d5dad0e2bd78792af64e6b1cfa40ea65b392fc /llvm/test | |
| parent | c5acee0f20f0ea73df77c3379ef051a8746c7c1e (diff) | |
| download | bcm5719-llvm-7ed0b5235a2d97bf8d81e36401478ce056152152.tar.gz bcm5719-llvm-7ed0b5235a2d97bf8d81e36401478ce056152152.zip | |
R600/SI: Lower 64-bit immediates using REG_SEQUENCE
llvm-svn: 205561
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/R600/fconst64.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/R600/trunc.ll | 5 |
2 files changed, 5 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/R600/fconst64.ll b/llvm/test/CodeGen/R600/fconst64.ll index 5c5ee7e9091..6c2a9034b87 100644 --- a/llvm/test/CodeGen/R600/fconst64.ll +++ b/llvm/test/CodeGen/R600/fconst64.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s ; CHECK: @fconst_f64 -; CHECK: V_MOV_B32_e32 {{v[0-9]+}}, 0.000000e+00 -; CHECK-NEXT: V_MOV_B32_e32 {{v[0-9]+}}, 2.312500e+00 +; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 1075052544 +; CHECK-DAG: S_MOV_B32 {{s[0-9]+}}, 0 define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) { %r1 = load double addrspace(1)* %in diff --git a/llvm/test/CodeGen/R600/trunc.ll b/llvm/test/CodeGen/R600/trunc.ll index 8a759dc21c0..43c06ebbdb4 100644 --- a/llvm/test/CodeGen/R600/trunc.ll +++ b/llvm/test/CodeGen/R600/trunc.ll @@ -31,8 +31,9 @@ define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) { ; SI-LABEL: @trunc_shl_i64: ; SI: S_LOAD_DWORDX2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, -; SI: V_ADD_I32_e32 v[[LO_ADD:[0-9]+]], s[[LO_SREG]], -; SI: V_LSHL_B64 v{{\[}}[[LO_VREG:[0-9]+]]:{{[0-9]+\]}}, v{{\[}}[[LO_ADD]]:{{[0-9]+\]}}, 2 +; SI: S_ADD_I32 s[[LO_ADD:[0-9]+]], s[[LO_SREG]], +; SI: S_LSHL_B64 s{{\[}}[[LO_SREG2:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_ADD]]:{{[0-9]+\]}}, 2 +; SI: V_MOV_B32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]] ; SI: BUFFER_STORE_DWORD v[[LO_VREG]], define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) { %aa = add i64 %a, 234 ; Prevent shrinking store. |
