summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* [MC] Function stack size section.Sean Eveson2017-11-301-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | Re applying after fixing issues in the diff, sorry for any painful conflicts/merges! Original RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-August/117028.html This change adds a '.stack-size' section containing metadata on function stack sizes to output ELF files behind the new -stack-size-section flag. The section contains pairs of function symbol references (8 byte) and stack sizes (unsigned LEB128). The contents of this section can be used to measure changes to stack sizes between different versions of the compiler or a source base. The advantage of having a section is that we can extract this information when examining binaries that we didn't build, and it allows users and tools easy access to that information just by referencing the binary. There is a follow up change to add an option to clang. Thanks. Reviewers: hfinkel, MatzeB Reviewed By: MatzeB Subscribers: thegameg, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D39788 llvm-svn: 319430
* Revert r319423: [MC] Function stack size section.Sean Eveson2017-11-301-30/+0
| | | | | | I messed up the diff. llvm-svn: 319429
* [ARM GlobalISel] Bail out for byvalDiana Picus2017-11-301-0/+15
| | | | | | | Fallback if we have a byval parameter or argument since we don't support them yet. llvm-svn: 319428
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-3041-208/+208
| | | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
* [MC] Function stack size section.Sean Eveson2017-11-301-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Original RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-August/117028.html I wasn't sure who to put as reviewers, so please add/remove people as appropriate. This change adds a '.stack-size' section containing metadata on function stack sizes to output ELF files behind the new -stack-size-section flag. The section contains pairs of function symbol references (8 byte) and stack sizes (unsigned LEB128). The contents of this section can be used to measure changes to stack sizes between different versions of the compiler or a source base. The advantage of having a section is that we can extract this information when examining binaries that we didn't build, and it allows users and tools easy access to that information just by referencing the binary. There is a follow up change to add an option to clang. Thanks. Reviewers: hfinkel, MatzeB Reviewed By: MatzeB Subscribers: thegameg, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D39788 llvm-svn: 319423
* Support generic lowering of vector bswapSerge Guelton2017-11-301-0/+50
| | | | llvm-svn: 319419
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-301-6/+6
| | | | llvm-svn: 319418
* [dsymutil] Upstream getBundleInfo implementationJonas Devlieghere2017-11-302-0/+50
| | | | | | | | | | | | | This patch implements `getBundleInfo`, which uses CoreFoundation to obtain information about the CFBundle. This information is needed to populate the Plist in the dSYM bundle. This change only applies to darwin and is an NFC as far as other platforms are concerned. Differential revision: https://reviews.llvm.org/D40244 llvm-svn: 319416
* Revert rL319407: [SROA] enable splitting for non-whole-alloca loads and stores Hiroshi Inoue2017-11-303-59/+17
| | | | | | This reverts commit rL319407 due to failures in some buildbot. llvm-svn: 319410
* [SystemZ] Bugfix in adjustSubwordCmp.Jonas Paulsson2017-11-301-0/+192
| | | | | | | | | | | | | | | | Csmith generated a program where a store after load to the same address did not get chained after the new load created during DAG legalizing, and so performed an illegal overwrite of the expected value. When the new zero-extending load is created, the chain users of the original load must be updated, which was not done previously. A similar case was also found and handled in lowerBITCAST. Review: Ulrich Weigand https://reviews.llvm.org/D40542 llvm-svn: 319409
* [SROA] enable splitting for non-whole-alloca loads and storesHiroshi Inoue2017-11-303-17/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, SROA splits loads and stores only when they are accessing the whole alloca. This patch relaxes this limitation to allow splitting a load/store if all other loads and stores to the alloca are disjoint to or fully included in the current load/store. If there is no other load or store that crosses the boundary of the current load/store, the current splitting implementation works as is. The whole-alloca loads and stores meet this new condition and so they are still splittable. Here is a simplified motivating example. struct record { long long a; int b; int c; }; int func(struct record r) { for (int i = 0; i < r.c; i++) r.b++; return r.b; } When updating r.b (or r.c as well), LLVM generates redundant instructions on some platforms (such as x86_64, ppc64); here, r.b and r.c are packed into one 64-bit GPR when the struct is passed as a method argument. With this patch, the above example is compiled into only few instructions without loop. Without the patch, unnecessary loop-carried dependency is introduced by SROA and the loop cannot be eliminated by the later optimizers. Differential Revision: https://reviews.llvm.org/D32998 llvm-svn: 319407
* [X86] Optimize avx2 vgatherqps for v2f32 with v2i64 index type.Craig Topper2017-11-301-8/+6
| | | | | | Normal type legalization will widen everything. This requires forcing 0s into the mask register. We can instead choose the form that only reads 2 elements without zeroing the mask. llvm-svn: 319406
* [X86] Make sure we don't remove sign extends of masks with AVX2 masked gathers.Craig Topper2017-11-301-4/+48
| | | | | | We don't use k-registers and instead use the MSB so we need to make sure we sign extend the mask to the msb. llvm-svn: 319405
* - Removed unused lamba (IsReturnBlock) causing build bots to fail for r319398Graham Yiu2017-11-302-0/+289
| | | | | | - Added lit testcases that were supposed to be part of r319398 llvm-svn: 319399
* AMDGPU: Allow negative MUBUF vaddr for gfx9Matt Arsenault2017-11-302-243/+138
| | | | | | | | GFX9 does not enable bounds checking for the resource descriptors used for private access, so it should be OK to use vaddr with a potentially negative value. llvm-svn: 319393
* Check alignment in getSectionContentsAsArray.Rafael Espindola2017-11-301-0/+21
| | | | | | | | While the ArrayRef can technically have unaligned data, it would be extremely surprising if iterating over it caused undefined behavior when a reference to the underlying type was bound. llvm-svn: 319392
* [Coverage] Use the most-recent completed region count (PR35437)Vedant Kumar2017-11-301-1/+3
| | | | | | | | | | | | | | | This is a fix for the coverage segment builder. If multiple regions must be popped off the active stack at once, and more than one of them end at the same location, emit a segment using the count from the most-recent completed region. Fixes PR35437, rdar://35760630 Testing: invoked llvm-cov on a stage2 build of clang, additional unit tests, check-profile llvm-svn: 319391
* First step towards more human-friendly PPC assembler output:Joerg Sonnenberger2017-11-291-0/+3
| | | | | | | | | | | | | | - add -ppc-reg-with-percent-prefix option to use %r3 etc as register names - split off logic for Darwinish verbose conditional codes into a helper function - be explicit about Darwin vs AIX vs GNUish assembler flavors Based on the patch from Alexandre Yukio Yamashita Differential Revision: https://reviews.llvm.org/D39016 llvm-svn: 319381
* [SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint ↵Craig Topper2017-11-292-20/+5
| | | | | | | | | | | | to insert an assertsext/assertzext based on the original type If we put in an assertsext/zext here, we're able to generate better truncate code using pack on pre-avx512 targets. Similar is already done during type legalization. This is the equivalent for op legalization Differential Revision: https://reviews.llvm.org/D40591 llvm-svn: 319368
* [WebAssembly] Fix fptoui lowering boundsDan Gohman2017-11-291-48/+52
| | | | | | | To fully avoid trapping on wasm, fptoui needs a second check to ensure that the operand isn't below the supported range. llvm-svn: 319354
* [Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek2017-11-291-1/+1
| | | | llvm-svn: 319352
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION)Simon Pilgrim2017-11-291-6/+6
| | | | | | Accidental commit of incomplete patch llvm-svn: 319346
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-291-6/+6
| | | | llvm-svn: 319338
* [X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions ↵Simon Pilgrim2017-11-292-146/+146
| | | | | | scheduler classes llvm-svn: 319337
* [ARM][DAG] Revert Disable post-legalization store merge for ARMNirav Dave2017-11-291-31/+19
| | | | | | | | Partially reverting enabling of post-legalization store merge (r319036) for just ARM backend as it is causing incorrect code in some Thumb2 cases. llvm-svn: 319331
* [Power9] add more tests for D38287; NFCZaara Syeda2017-11-291-0/+248
| | | | llvm-svn: 319328
* [InstCombine] add tests for select-of-constants; NFCSanjay Patel2017-11-291-0/+33
| | | | | | | | | These are variants of a test that was originally added in: https://reviews.llvm.org/rL75531 ...but removed with: https://reviews.llvm.org/rL159230 llvm-svn: 319327
* Add opt-viewer testingAdam Nemet2017-11-2911-0/+1111
| | | | | | | | | | | | | | | | | | | | Detects whether we have the Python modules (pygments, yaml) required by opt-viewer and hooks this up to REQUIRES. This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer testing). It's also related to https://github.com/apple/swift/pull/12938 and the idea is to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake. Differential Revision: https://reviews.llvm.org/D40202 Fixes since the first commit: 1. Disable syntax highlighting as different versions of pygments generate different HTML 2. Use llvm-cxxfilt from the build llvm-svn: 319324
* Reverted r319315 because of unused functions (due to PPR not yet beingSander de Smalen2017-11-292-29/+0
| | | | | | used by any instructions). llvm-svn: 319321
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-11-292-0/+29
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 319315
* [ARM GlobalISel] Fix selecting G_BRCONDDiana Picus2017-11-292-2/+2
| | | | | | | | | | | | | When lowering a G_BRCOND, we generate a TSTri of the condition against 1, which sets the flags, and then a Bcc which branches based on the value of the flags. Unfortunately, we were using the wrong condition code to check whether we need to branch (EQ instead of NE), which caused all our branches to do the opposite of what they were intended to do. This patch fixes the issue by using the correct condition code. llvm-svn: 319313
* [ARM] Add support for armv7e-m to the .arch directiveOliver Stannard2017-11-293-0/+69
| | | | | | | | | | | This will allow compilation of assembly files targeting armv7e-m without having to specify the Tag_CPU_arch attribute as a workaround. Differential revision: https://reviews.llvm.org/D40370 Patch by Ian Tessier! llvm-svn: 319303
* [CGP] Fix common type handling in optimizeMemoryInstSerguei Katkov2017-11-291-0/+33
| | | | | | | | | | | | | | | | | If common type is different we should bail out due to we will not be able to create a select or Phi of these values. Basically it is done in ExtAddrMode::compare however it does not work if we handle the null first and then two values of different types. so add a check in initializeMap as well. The check in ExtAddrMode::compare is used as earlier bail out. Reviewers: reames, john.brawn Reviewed By: john.brawn Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40479 llvm-svn: 319292
* [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.Sean Fertile2017-11-291-0/+33
| | | | | | | | | | | | Separate the handling of AND/AND8 out from PHI/OR/ISEL checking. The reasoning is the others need all their operands to be sign/zero extended for their output to also be sign/zero extended. This is true for AND and sign-extension, but for zero-extension we only need at least one of the input operands to be zero extended for the result to also be zero extended. Differential Revision: https://reviews.llvm.org/D39078 llvm-svn: 319289
* AMDGPU: Use stricter regexes for add instructionsMatt Arsenault2017-11-296-66/+66
| | | | | | | Match the entire _co as one optional piece rather than a set of characters to match multiple times. llvm-svn: 319275
* llvm-dwarfdump: honor the --show-children option when dumping a specific DIE.Adrian Prantl2017-11-291-0/+6
| | | | llvm-svn: 319271
* AMDGPU: Select DS insts without m0 initializationMatt Arsenault2017-11-2925-524/+1623
| | | | | | | | | GFX9 stopped using m0 for most DS instructions. Select a different instruction without the use. I think this will be less error prone than trying to manually maintain m0 uses as needed. llvm-svn: 319270
* [X86] Promote fp_to_sint v16f32->v16i16/v16i8 to avoid scalarization.Craig Topper2017-11-292-97/+6
| | | | llvm-svn: 319266
* Revert "Add opt-viewer testing"Adam Nemet2017-11-2911-1111/+0
| | | | | | | | This reverts commit r319188. Breaks when c++filt is not available. llvm-svn: 319262
* [X86] Add test cases for fptosi v16f32->v16i8/v16i16 to show scalarization.Craig Topper2017-11-291-0/+112
| | | | llvm-svn: 319261
* [X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of ↵Craig Topper2017-11-282-6/+6
| | | | | | | | | | legal. Fix infinite loop in op legalization when promotion requires 2 steps. Previously we had an isel pattern to add the truncate. Instead use Promote to add the truncate to the DAG before isel. The Promote legalization code had to be updated to prevent an infinite loop if promotion took multiple steps because it wasn't remembering the previously tried value. llvm-svn: 319259
* [X86] Regenerate avx512-schedule test.Craig Topper2017-11-281-2/+2
| | | | | | For some reason some sqrt instructions were missing the scheduling comments. llvm-svn: 319258
* AMDGPU: Enable IPRAMatt Arsenault2017-11-287-14/+15
| | | | llvm-svn: 319256
* [X86] Tag CLFLUSHOPT with same scheduling behaviour as CLFLUSHSimon Pilgrim2017-11-281-2/+2
| | | | llvm-svn: 319253
* [globalisel][tablegen] Fix PR35375 by sign-extending the table value to ↵Daniel Sanders2017-11-281-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | match getConstantVRegVal() Summary: From the bug report: > The problem is that it fails when trying to compare -65536 (or 4294901760) to 0xFFFF,0000. This is because the > constant in the instruction is sign extended to 64 bits (0xFFFF,FFFF,FFFF,0000) and then compared to the non > extended 64 bit version expected by TableGen. > > In contrast, the DAGISelEmitter generates special code for AND immediates (OPC_CheckAndImm), which does not > sign extend. This patch doesn't introduce the special case for AND (and OR) immediates since the majority of it is related to handling known bits that have no effect on the result and GlobalISel doesn't detect known-bits at this time. Instead this patch just ensures that the immediate is extended consistently on both sides of the check. Thanks to Diana Picus for the detailed bug report. Reviewers: rovka Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40532 llvm-svn: 319252
* [X86] Add CLFLUSHOPT schedule testsSimon Pilgrim2017-11-281-0/+36
| | | | llvm-svn: 319250
* [X86] Test clflushopt intrinsic on 32 and 64-bit targetsSimon Pilgrim2017-11-281-6/+12
| | | | llvm-svn: 319247
* Remove this testAdam Nemet2017-11-281-25/+0
| | | | | | After r319235, we no longer generate this remark. llvm-svn: 319242
* Demote this opt remark to DEBUG.Adam Nemet2017-11-281-1/+0
| | | | | | | | | | | | | | | | | | From a random opt-stat output: Top 10 remarks: tailcallelim/tailcall 53% inline/AlwaysInline 13% gvn/LoadClobbered 13% inline/Inlined 8% inline/TooCostly 2% inline/NoDefinition 2% licm/LoadWithLoopInvariantAddressInvalidated 2% licm/Hoisted 1% asm-printer/InstructionCount 1% prologepilog/StackSize 1% llvm-svn: 319235
* [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, ↵Daniel Sanders2017-11-283-2/+293
| | | | | | | | | | G_ATOMICRMW_* rules from SelectionDAG. GIM_CheckNonAtomic has been replaced by GIM_CheckAtomicOrdering to allow it to support a wider range of orderings. This has then been used to import patterns using nodes such as atomic_cmp_swap, atomic_swap, and atomic_load_*. llvm-svn: 319232
OpenPOWER on IntegriCloud