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* [Hexagon] Insert CFI instructions before throwing callsKrzysztof Parzyszek2016-07-281-0/+72
| | | | | | | | Normally, CFI instructions should be inserted after allocframe, but if allocframe is in the same packet with a call, the CFI instructions should be inserted before that packet. llvm-svn: 277020
* [AArch64][GlobalISel] Select G_BR.Ahmed Bougacha2016-07-281-0/+18
| | | | | | | This is the first unsized instruction we support; move down the 'sized' check to binops. llvm-svn: 277007
* [MIRParser] Accept unsized generic instructions.Ahmed Bougacha2016-07-282-22/+19
| | | | | | | Since r276158, we require generic instructions to have a sized type. G_BR doesn't; relax the restriction. llvm-svn: 277006
* [AArch64][GlobalISel] Select GPR G_SUB.Ahmed Bougacha2016-07-281-0/+51
| | | | llvm-svn: 277003
* [AArch64][GlobalISel] Select GPR G_AND.Ahmed Bougacha2016-07-281-0/+51
| | | | llvm-svn: 277002
* [GlobalISel] Remove types on selected insts instead of using LLT().Ahmed Bougacha2016-07-281-2/+2
| | | | | | | | | | LLT() has a particular meaning: it's one invalid type. But we really want selected instructions to have no type whatsoever. Also verify that types don't linger after ISel, and enable the verifier on the AArch64 select test. llvm-svn: 277001
* [AArch64][GlobalISel] Remove 'alignment' from MIR tests. NFC.Ahmed Bougacha2016-07-281-4/+0
| | | | llvm-svn: 277000
* AMDGPU : Add intrinsics for compare with the full wavefront resultWei Ding2016-07-282-0/+400
| | | | | | Differential Revision: http://reviews.llvm.org/D22482 llvm-svn: 276998
* Revert r276982 and r276984: [mips][fastisel] Handle 0-4 arguments without ↵Daniel Sanders2016-07-2824-50/+50
| | | | | | | | | SelectionDAG It seems that the stack offset in callabi.ll varies between machines. I'll look into it. llvm-svn: 276989
* [X86] Remove CustomInserter for FMA3 instructions. Looks like since we got ↵Craig Topper2016-07-281-2/+2
| | | | | | | | full commuting support for FMAs after this was added, the coalescer can now get this right on its own. Differential Revision: https://reviews.llvm.org/D22799 llvm-svn: 276987
* [mips][fastisel] Handle 0-4 arguments without SelectionDAG.Daniel Sanders2016-07-2824-50/+50
| | | | | | | | | | | | | | | | | | | Summary: Implements fastLowerArguments() to avoid the need to fall back on SelectionDAG for 0-4 argument functions that don't do tricky things like passing double in a pair of i32's. This allows us to move all except one test to -fast-isel-abort=3. The remaining one has function prototypes of the form 'i32 (i32, double, double)' which requires floats to be passed in GPR's. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D22680 llvm-svn: 276982
* AMDGPU: add execfix flag to SI_ELSENicolai Haehnle2016-07-281-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: SI_ELSE is lowered into two parts: s_or_saveexec_b64 dst, src (at the start of the basic block) s_xor_b64 exec, exec, dst (at the end of the basic block) The idea is that dst contains the exec mask of the preceding IF block. It can happen that SIWholeQuadMode decides to switch from WQM to Exact mode inside the basic block that contains SI_ELSE, in which case it introduces an instruction s_and_b64 exec, exec, s[...] which masks out bits that can correspond to both the IF and the ELSE paths. So the resulting sequence must be: s_or_savexec_b64 dst, src s_and_b64 exec, exec, s[...] <-- added by SIWholeQuadMode s_and_b64 dst, dst, exec <-- added by SILowerControlFlow s_xor_b64 exec, exec, dst Whether to add the additional s_and_b64 dst, dst, exec is currently determined via the ExecModified tracking. With this change, it is instead determined by an additional flag on SI_ELSE which is set by SIWholeQuadMode. Finally: It also occured to me that an alternative approach for the long run is for SILowerControlFlow to unconditionally emit s_or_saveexec_b64 dst, src ... s_and_b64 dst, dst, exec s_xor_b64 exec, exec, dst and have a pass that detects and cleans up the "redundant AND with exec" pattern where possible. This could be useful anyway, because we also add instructions s_and_b64 vcc, exec, vcc before s_cbranch_scc (in moveToALU), and those are often redundant. I have some pending changes to how KILL is lowered that could also benefit from such a cleanup pass. In any case, this current patch could help in the short term with the whole ExecModified business. Reviewers: tstellarAMD, arsenm Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D22846 llvm-svn: 276972
* [ConstantFolding] Don't bail on folding if ConstantFoldConstantExpression failsDavid Majnemer2016-07-281-2/+1
| | | | | | | | | | | | When folding an expression, we run ConstantFoldConstantExpression on each operand of that expression. However, ConstantFoldConstantExpression can fail and retur nullptr. Previously, we would bail on further refining the expression. Instead, use the original operand and see if we can refine a later operand. llvm-svn: 276959
* [CodeView] Don't crash on functions without subprogramsDavid Majnemer2016-07-282-1/+45
| | | | | | | | | A function may have instructions annotated with debug info without having a subprogram. This fixes PR28747. llvm-svn: 276956
* [InstCombine] Handle failures from ConstantFoldConstantExpressionDavid Majnemer2016-07-281-0/+8
| | | | | | | | ConstantFoldConstantExpression returns null when folding fails. This fixes PR28745. llvm-svn: 276952
* Fix the assertion error in collectLoopUniforms caused by empty Worklist ↵Wei Mi2016-07-271-0/+19
| | | | | | | | | | before expanding. Contributed-by: David Callahan Differential Revision: https://reviews.llvm.org/D22886 llvm-svn: 276943
* [CFLAA] Add getModRefBehavior to CFLAnders.George Burgess IV2016-07-276-0/+25
| | | | | | | | | | | This patch lets CFLAnders respond to mod-ref queries. It also includes a small bugfix to CFLSteens. Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22823 llvm-svn: 276939
* [llvm-cov] Add a debug mode for source range highlighting (in html)Vedant Kumar2016-07-271-18/+19
| | | | | | | llvm-cov's `-dump' option now emits information which helps debug source range highlighting in html mode. llvm-svn: 276924
* [LSV] Don't assume that bitcast ops are Instructions.Justin Lebar2016-07-271-0/+14
| | | | | | | | | | | | | | Summary: When we ask the builder to create a bitcast on a constant, we get back a constant, not an instruction. Reviewers: asbirlea Subscribers: jholewinski, mzolotukhin, llvm-commits, arsenm Differential Revision: https://reviews.llvm.org/D22878 llvm-svn: 276922
* [Hexagon] Find speculative loop preheader in hardware loop generationKrzysztof Parzyszek2016-07-271-0/+44
| | | | | | | | Before adding a new preheader block, check if there is a candidate block where the loop setup could be placed speculatively. This will be off by default. llvm-svn: 276919
* [Hexagon] Do not optimize volatile stack spill slotsKrzysztof Parzyszek2016-07-271-0/+29
| | | | llvm-svn: 276916
* Revert EH-specific checks in BranchFolding that were causing blow ups in ↵Andrew Kaylor2016-07-272-27/+28
| | | | | | | | compile time. Differential Revision: https://reviews.llvm.org/D22839 llvm-svn: 276898
* GlobalISel: support zero-sized allocasTim Northover2016-07-271-0/+3
| | | | | | | All allocas must be at least 1 byte at the MachineIR level so we allocate just one byte. llvm-svn: 276897
* [MC][X86] Fix Intel Operand assembly parsing for .set idsNirav Dave2016-07-272-0/+18
| | | | | | | | | | | | | Fix intel syntax special case identifier operands that refer to a constant (e.g. .set <ID> n) to be interpreted as immediate not memory in parsing. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22585 llvm-svn: 276895
* [X86][SSE] Updated test so that both are applying the post-multiplySimon Pilgrim2016-07-271-11/+14
| | | | | | This is to ensure that there are no diffs other than due to buildvector/legalization llvm-svn: 276882
* [ARM] Check that the thumb COFF segment flag gets set on thumb windowsRenato Golin2016-07-271-0/+16
| | | | | | Patch by Martin Storsjö. llvm-svn: 276877
* [GlobalISel] Introduce an instruction selector.Ahmed Bougacha2016-07-271-0/+118
| | | | | | | | And implement it for AArch64, supporting x/w ADD/OR. Differential Revision: https://reviews.llvm.org/D22373 llvm-svn: 276875
* [mips][ias] Check '$rs = $rd' constraints when both registers are in AsmText.Daniel Sanders2016-07-274-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is one possible solution to the problem of ignoring constraints that Simon raised in D21473 but it's a bit of a hack. The integrated assembler currently ignores violations of the tied register constraints when the operands involved in a tie are both present in the AsmText. For example, 'dati $rs, $rt, $imm' with the '$rs = $rt' will silently replace $rt with $rs. So 'dati $2, $3, 1' is processed as if the user provided 'dati $2, $2, 1' without any diagnostic being emitted. This is difficult to solve properly because there are multiple parts of the matcher that are silently forcing these constraints to be met. Tied operands are rendered to instructions by cloning previously rendered operands but this is unnecessary because the matcher was already instructed to render the operand it would have cloned. This is also unnecessary because earlier code has already replaced the MCParsedOperand with the one it was tied to (so the parsed input is matched as if it were 'dati <RegIdx 2>, <RegIdx 2>, <Imm 1>'). As a result, it looks like fixing this properly amounts to a rewrite of the tied operand handling which affects all targets. This patch however, merely inserts a checking hook just before the substitution of MCParsedOperands and the Mips target overrides it. It's not possible to accurately check the registers are the same this early (because numeric registers haven't been bound to a register class yet) so it cheats a bit and checks that the tokens that produced the operand are lexically identical. This works because tied registers need to have the same register class but it does have a flaw. It will reject 'dati $4, $a0, 1' for violating the constraint even though $a0 ends up as the same register as $4. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D21994 llvm-svn: 276867
* [test/gold] Add gold test subdirectory tests needing v1.12 (or higher)Teresa Johnson2016-07-273-0/+63
| | | | | | | | | | | | | | | | Summary: As discussed in the review for D22677, added a subdirectory to enable tests that require at least version 1.12 of gold. Add an initial test requiring this version. Reviewers: davidxl, mehdi_amini Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D22827 llvm-svn: 276860
* [ARM] Set a non-conflicting comment character for assembly in MSVC modeRenato Golin2016-07-271-0/+13
| | | | | | | | | | | | | | | | | | | | | | | Currently, for ARMCOFFMCAsmInfoMicrosoft, no comment character is set, thus the idefault, '#', is used. The hash character doesn't work as comment character in ARM assembly, since '#' is used for immediate values. The comment character is set to ';', which is the comment character used by MS armasm.exe. (The microsoft armasm.exe uses a different directive syntax than what LLVM currently supports though, similar to ARM's armasm.) This allows inline assembly with immediate constants to be built (and brings the assembly output from clang -S closer to being possible to assemble). A test is added that verifies that ';' is correctly interpreted as comments in this mode, and verifies that assembling code that includes literal constants with a '#' works. Patch by Martin Storsjö. llvm-svn: 276859
* [ARM] Adds test for immediate encodingRenato Golin2016-07-271-0/+29
| | | | | | | | | The encoding of expressions as immediates wasn't correct, and was reported in PR23000. However, we have done some refactoring on how immediates are handled and now it seems the problem is fixed. This is a test just to make sure it won't regress again. llvm-svn: 276858
* [DAGCombiner] Use APInt directly to detect out of range shift constantsSimon Pilgrim2016-07-271-9/+94
| | | | | | | | Using getZExtValue() will assert if the value doesn't fit into uint64_t - SHL was already doing this, I've just updated ASHR/LSHR to match As mentioned on D22726 llvm-svn: 276855
* [MC] Add command-line option to choose the max nest level in asm macros.Davide Italiano2016-07-271-0/+20
| | | | | | | Submitted by: t83wCSLq Differential Revision: https://reviews.llvm.org/D22313 llvm-svn: 276842
* GVN-hoist: improve code generation for recursive GEPsSebastian Pop2016-07-271-0/+103
| | | | | | | | | | | | | | | | | | | When loading or storing in a field of a struct like "a.b.c", GVN is able to detect the equivalent expressions, and GVN-hoist would fail in the code generation. This is because the GEPs are not hoisted as scalar operations to avoid moving the GEPs too far from their ld/st instruction when the ld/st is not movable. So we end up having to generate code for the GEP of a ld/st when we move the ld/st. In the case of a GEP referring to another GEP as in "a.b.c" we need to code generate all the GEPs necessary to make all the operands available at the new location for the ld/st. With this patch we recursively walk through the GEP operands checking whether all operands are available, and in the case of a GEP operand, it recursively makes all its operands available. Code generation happens from the inner GEPs out until reaching the GEP that appears as an operand of the ld/st. Differential Revision: https://reviews.llvm.org/D22599 llvm-svn: 276841
* [llvm-cov] Escape '\' in strings when emitting JSONVedant Kumar2016-07-271-1/+3
| | | | | | | Test that Windows path separators are escaped properly. Add a round-trip test to verify the JSON produced by the exporter. llvm-svn: 276832
* [ConstantFolding] Correctly handle failures in ↵David Majnemer2016-07-271-0/+14
| | | | | | | | | | | ConstantFoldConstantExpressionImpl Failures in ConstantFoldConstantExpressionImpl were ignored causing crashes down the line. This fixes PR28725. llvm-svn: 276827
* Reverting r276771 due to MSan failures.Andrew Kaylor2016-07-272-6/+0
| | | | llvm-svn: 276824
* AMDGPU: Use rcp for fdiv 1, x with fpmath metadataMatt Arsenault2016-07-263-18/+94
| | | | | | | Using rcp should be OK for safe math usually, so this should not be replacing the original fdiv. llvm-svn: 276823
* Revert r276136 "Use ValueOffsetPair to enhance value reuse during SCEV ↵Hans Wennborg2016-07-261-44/+0
| | | | | | | | | | expansion." It causes Clang tests to fail after Windows self-host (PR28705). (Also reverts follow-up r276139.) llvm-svn: 276822
* AMDGPU: Add more tests for LDS size with occupancyMatt Arsenault2016-07-261-2/+149
| | | | llvm-svn: 276821
* Retry: [llvm-cov] Add support for exporting coverage data to JSONVedant Kumar2016-07-2612-0/+266
| | | | | | | | | | | | | | | | | | | | | | | | This enables users to export coverage information as portable JSON for use by analysis tools and storage in document based databases. The export sub-command is invoked just like the others: llvm-cov export -instr-profile path/to/foo.profdata path/to/foo.binary The resulting JSON contains a list of files and functions. Every file object contains a list of segments, expansions, and a summary of the file's region, function, and line coverage. Every function object contains the function's name and regions. There is also a total summary for the entire object file. Changes since the initial commit (r276813): - Fixed the regexes in the tests to handle Windows filepaths. Patch by Eddie Hurtig! Differential Revision: https://reviews.llvm.org/D22651 llvm-svn: 276818
* Revert "[llvm-cov] Add support for exporting coverage data to JSON"Vedant Kumar2016-07-2612-267/+0
| | | | | | | | | This reverts commit r276813. The Windows bots are complaining about some of the filename regexes in the tests: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/5299 llvm-svn: 276816
* MIRParser: Use dot instead of colon to mark subregistersMatthias Braun2016-07-267-91/+91
| | | | | | | | | | | | | | | | | Change the syntax to use `%0.sub8` to denote a subregister. This seems like a more natural fit to denote subregisters; I also plan to introduce a new ":classname" syntax in upcoming patches to denote the register class of a vreg. Note that this commit disallows plain identifiers to start with a '.' character. This shouldn't affect anything as external names/IR references are all prefixed with '$'/'%', plain identifiers are only used for instruction names, register mask names and subreg indexes. Differential Revision: https://reviews.llvm.org/D22390 llvm-svn: 276815
* [llvm-cov] Add support for exporting coverage data to JSONVedant Kumar2016-07-2612-0/+267
| | | | | | | | | | | | | | | | | | | | This enables users to export coverage information as portable JSON for use by analysis tools and storage in document based databases. The export sub-command is invoked just like the others: llvm-cov export -instr-profile path/to/foo.profdata path/to/foo.binary The resulting JSON contains a list of files and functions. Every file object contains a list of segments, expansions, and a summary of the file's region, function, and line coverage. Every function object contains the function's name and regions. There is also a total summary for the entire object file. Patch by Eddie Hurtig! Differential Revision: https://reviews.llvm.org/D22651 llvm-svn: 276813
* [Hexagon] Post-increment loads/stores enhancementsKrzysztof Parzyszek2016-07-261-0/+69
| | | | | | | - Generate vector post-increment stores more aggressively. - Predicate post-increment and vector stores in early if-conversion. llvm-svn: 276800
* GlobalISel: add generic load and store instructions.Tim Northover2016-07-261-0/+30
| | | | | | | Pretty straightforward, the only oddity is the MachineMemOperand (which it's surprisingly difficult to share code for). llvm-svn: 276799
* [Hexagon] Gracefully handle reg class mismatch in HexagonLoopRescheduleKrzysztof Parzyszek2016-07-261-0/+30
| | | | llvm-svn: 276793
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-261-0/+208
| | | | | | | | | | | | | | | | | | | Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. llvm-svn: 276792
* [Hexagon] Bitwise operations for insert/extract word not simplifiedKrzysztof Parzyszek2016-07-262-4/+47
| | | | | | | Change the bit simplifier to generate REG_SEQUENCE instructions in addition to COPY, which will handle cases of word insert/extract. llvm-svn: 276787
* Fix NVPTX/call-with-alloca-buffer.ll after r276777.Justin Lebar2016-07-261-4/+2
| | | | | | | r276777 makes InstSimplify stronger, letting it see through some unnecessary addrspace casts. llvm-svn: 276786
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