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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-07-28 17:15:15 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-07-28 17:15:15 +0000 |
| commit | 8550509b64e671e4ead8dbc0628c54b5f856875f (patch) | |
| tree | 20c06cfd24dacb6020139d15552d892f6025b0d1 /llvm/test | |
| parent | d760de0b325ef65dfcf7e0d4b6e72a7f02c17725 (diff) | |
| download | bcm5719-llvm-8550509b64e671e4ead8dbc0628c54b5f856875f.tar.gz bcm5719-llvm-8550509b64e671e4ead8dbc0628c54b5f856875f.zip | |
[AArch64][GlobalISel] Select G_BR.
This is the first unsized instruction we support; move down the
'sized' check to binops.
llvm-svn: 277007
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index 2924b543fe2..555956c9745 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -20,6 +20,8 @@ define void @and_s32_gpr() { ret void } define void @and_s64_gpr() { ret void } + define void @unconditional_br() { ret void } + ... --- @@ -214,3 +216,19 @@ body: | %0(64) = COPY %x0 %1(64) = G_AND s64 %0, %0 ... + +--- +# CHECK-LABEL: name: unconditional_br +name: unconditional_br +isSSA: true + +# CHECK: body: +# CHECK: bb.0: +# CHECK: successors: %bb.0 +# CHECK: B %bb.0 +body: | + bb.0: + successors: %bb.0 + + G_BR unsized %bb.0 +... |
