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* Add a testcase for r207627.James Molloy2014-04-301-0/+4
| | | | llvm-svn: 207697
* Use the new StringTableBuilder in yaml2elfHans Wennborg2014-04-302-8/+8
| | | | | | http://reviews.llvm.org/D3574 llvm-svn: 207694
* [X86] Never hoist the shift value of a shift instruction.Michael Zolotukhin2014-04-302-4/+24
| | | | | | | | | | | There is no need to check if we want to hoist the immediate value of an shift instruction. Simply return TCC_Free right away. This change is like r206101, but for X86. rdar://problem/16190769 llvm-svn: 207692
* [IPO/MergeFunctions] changes so it doesn't try to bitcast a struct return ↵Carlo Kok2014-04-301-0/+40
| | | | | | type but instead recreates it with insert/extract value. llvm-svn: 207679
* IR: Conservatively verify inalloca argumentsDavid Majnemer2014-04-303-3/+16
| | | | | | | | | | | | Summary: Try to spot obvious mismatches with inalloca use. Reviewers: rnk Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3572 llvm-svn: 207676
* [mips] Add instruction alias (negu).Matheus Almeida2014-04-309-0/+18
| | | | | | | | | | | | Summary: negu $reg is equivalent to negu $reg, $reg. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3510 llvm-svn: 207673
* [mips] Add instruction alias (sltu).Matheus Almeida2014-04-309-0/+9
| | | | | | | | | | | | | | Summary: The pattern sltu $r1, $r2, $imm is found in handwritten assembly which is just a shorthand version of sltui $r1, $r2, $imm. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3508 llvm-svn: 207671
* ELFObjectWriter: deduplicate suffices in strtabHans Wennborg2014-04-3015-75/+96
| | | | | | | | | | | | | | | We already do this for shstrtab, so might as well do it for strtab. This extracts the string table building code into a separate class. The idea is to use it for other object formats too. I mostly wanted to do this for the general principle, but it does save a little bit on object file size. I tried this on a clang bootstrap and saved 0.54% on the sum of object file sizes (1.14 MB out of 212 MB for a release build). Differential Revision: http://reviews.llvm.org/D3533 llvm-svn: 207670
* ARM64: print fp immediates without using scientific notation.Tim Northover2014-04-308-24/+24
| | | | llvm-svn: 207669
* AArch64/ARM64: implement remaining TLS relocations (purely MC).Tim Northover2014-04-301-140/+309
| | | | llvm-svn: 207668
* AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.Tim Northover2014-04-305-494/+499
| | | | llvm-svn: 207667
* AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"Tim Northover2014-04-303-40/+42
| | | | | | | | | | It's been decided that in the future, the floating-point immediate in instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which has been implemented on AArch64 already but not ARM64. This fixes that issue. llvm-svn: 207666
* [mips] Add instruction alias (dsll and dsrl).Matheus Almeida2014-04-305-0/+10
| | | | | | | | | | | | | | Summary: The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3486 llvm-svn: 207664
* Relax the test a bit.Rafael Espindola2014-04-301-24/+24
| | | | | | | It is not relevant where the symbol and section names are stored, just their values. llvm-svn: 207662
* R600/SI: Use VALU instructions for copying i1 valuesTom Stellard2014-04-301-0/+39
| | | | | | | | | We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. llvm-svn: 207661
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-301-0/+28
| | | | llvm-svn: 207660
* [ARM64][fast-isel] Fast-isel doesn't know how to handle f128.Chad Rosier2014-04-301-1/+33
| | | | llvm-svn: 207659
* Rename the test, it is testing the symver directive.Rafael Espindola2014-04-301-0/+0
| | | | llvm-svn: 207658
* [mips] Add instruction alias (sll and srl).Matheus Almeida2014-04-309-0/+18
| | | | | | | | | | | | | | Summary: The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which is just a shorthand version of sllv/srlv $rd, $rt, $rs. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3483 llvm-svn: 207657
* [mips] Fix MipsLongBranch pass to work when the offset from the branch to theSasa Stankovic2014-04-302-16468/+127
| | | | | | | | | | | | | | target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
* [mips] Update tests with encoding information for slt, slti, sltiu and sltu.Matheus Almeida2014-04-309-36/+36
| | | | | | | | | | | | | | Summary: Also renamed non-portable register names (e.g. $t2) so that we don't end up with a different encoding for what appears to be an equivalent instruction. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3505 llvm-svn: 207655
* ARM64: enable AArch64's basic-a64-instructions testTim Northover2014-04-301-889/+1093
| | | | llvm-svn: 207650
* ARM64: print lsr instead of lsrv for variable shifts (etc)Tim Northover2014-04-303-26/+26
| | | | | | | The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
* ARM64: use 32-bit operations for uxtb & uxthTim Northover2014-04-301-2/+2
| | | | | | Testing will be enabled shortly with basic-a64-instructions.s llvm-svn: 207648
* AArch64/ARM64: copy support for bCC instead of b.CC across.Tim Northover2014-04-301-0/+37
| | | | llvm-svn: 207646
* AArch64/ARM64: use HS instead of CS & LO instead of CC.Tim Northover2014-04-305-24/+24
| | | | | | | | | On instructions using the NZCV register, a couple of conditions have dual representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and unsigned-lower/carry-clear). The first of these is more descriptive in most circumstances, so we should print it. llvm-svn: 207644
* [mips][msa] Fix vector insertions where the index is variableDaniel Sanders2014-04-302-0/+175
| | | | | | | | | | | | | | | | | | | | | Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
* ARM64: accept ELF-relocated load/store insts without a #.Tim Northover2014-04-301-21/+21
| | | | | | | E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax too. llvm-svn: 207639
* [mips] Add support for .cpload.Matheus Almeida2014-04-302-0/+48
| | | | | | | | | | | | | | | | | | | | Summary: This directive is used for setting up $gp in the beginning of a function. It expands to three instructions if PIC is enabled: lui $gp, %hi(_gp_disp) addui $gp, $gp, %lo(_gp_disp) addu $gp, $gp, $reg _gp_disp is a special symbol that the linker sets to the distance between the lui instruction and the context pointer (_gp). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3480 llvm-svn: 207637
* [mips] Emit all three relocation operations for each relocation entry on ↵Matheus Almeida2014-04-302-0/+4
| | | | | | | | | | | | | | | | Mips64 big-endian systems. Summary: The N64 ABI allows up to three operations to be specified per relocation record independently of the endianness. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3529 llvm-svn: 207636
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-3019-149/+149
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. llvm-svn: 207635
* ARM64: hexify printing various immediate operandsTim Northover2014-04-3011-158/+157
| | | | | | | | | | This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. llvm-svn: 207634
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-3011-51/+51
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
* [ARM64] Ensure arm64_be is dealt with when emitting debug info.James Molloy2014-04-301-0/+1
| | | | | | | This is a partial port of r204816 (cpirker "Elf support for MC-JIT runtime dynamic linker") from AArch64 to ARM64. llvm-svn: 207625
* ARM64: make sure FastISel uses a GPR64 source in 64-bit extensions.Tim Northover2014-04-301-8/+34
| | | | llvm-svn: 207620
* ARM: support stack probe emission for Windows on ARMSaleem Abdulrasool2014-04-301-0/+24
| | | | | | | | | | | | | | | | | This introduces the stack lowering emission of the stack probe function for Windows on ARM. The stack on Windows on ARM is a dynamically paged stack where any page allocation which crosses a page boundary of the following guard page will cause a page fault. This page fault must be handled by the kernel to ensure that the page is faulted in. If this does not occur and a write access any memory beyond that, the page fault will go unserviced, resulting in an abnormal program termination. The watermark for the stack probe appears to be at 4080 bytes (for accommodating the stack guard canaries and stack alignment) when SSP is enabled. Otherwise, the stack probe is emitted on the page size boundary of 4096 bytes. llvm-svn: 207615
* ARM: print COFF function header for Windows on ARMSaleem Abdulrasool2014-04-301-0/+45
| | | | | | | | | Emit the COFF header when printing out the function. This is important as the header contains two important pieces of information: the storage class for the symbol and the symbol type information. This bit of information is required for the linker to correctly identify the type of symbol that it is dealing with. llvm-svn: 207613
* ARM: partially handle 32-bit relocations for WoASaleem Abdulrasool2014-04-301-0/+27
| | | | | | | | | | | | | | | IMAGE_REL_ARM_MOV32T relocations require that the movw/movt pair-wise relocation is not split up and reordered. When expanding the mov32imm pseudo-instruction, create a bundle if the machine operand is referencing an address. This helps ensure that the relocatable address load is not reordered by subsequent passes. Unfortunately, this only partially handles the case as the Constant Island Pass occurs after the instructions are unbundled and does not properly handle bundles. That is a more fundamental issue with the pass itself and beyond the scope of this change. llvm-svn: 207608
* Implement X86 code generation for musttailReid Kleckner2014-04-293-4/+226
| | | | | | | | | | | | | | | | | | Currently, musttail codegen is relying on sibcall optimization, and reporting a fatal error if fails. Sibcall optimization fails when stack arguments need to be modified, which is insufficient for musttail. The logic for moving arguments in memory safely is already implemented for GuaranteedTailCallOpt. This change merely arranges for musttail calls to use it. No functional change for GuaranteedTailCallOpt. Reviewers: espindola Differential Revision: http://reviews.llvm.org/D3493 llvm-svn: 207598
* R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errorsTom Stellard2014-04-2925-25/+25
| | | | | | | | | | | | | | | | SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. llvm-svn: 207591
* R600/SI: Only select SALU instructions in the entry or exit blockTom Stellard2014-04-291-0/+27
| | | | | | | | SALU instructions ignore control flow, so it is not always safe to use them within branches. This is a partial solution to this problem until we can come up with something better. llvm-svn: 207590
* R600: optimize the UDIVREM 64 algorithmTom Stellard2014-04-291-0/+84
| | | | | | | | | | | | | | | | This is a squash of several optimization commits: - calculate DIV_Lo and DIV_Hi separately - use BFE_U32 if we are operating on 32bit values - use precomputed constants instead of shifting in UDVIREM - skip the first 32 iterations of udivrem v2: Check whether BFE is supported before using it Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207589
* Also handle ConstantAggregateZero when optimizing vpermilvar*.Rafael Espindola2014-04-291-0/+28
| | | | llvm-svn: 207582
* Two fixes to the vpermilvar optimization.Rafael Espindola2014-04-291-4/+4
| | | | | | | | The instcomine logic to handle vpermilvar's pd and 256 variants was incorrect. The _256 variants have indexes into the individual 128 bit lanes and in all cases it also has to mask out unused bits. llvm-svn: 207577
* Fix vectorization remarks.Diego Novillo2014-04-292-0/+92
| | | | | | | | | This patch changes the vectorization remarks to also inform when vectorization is possible but not beneficial. Added tests to exercise some loop remarks. llvm-svn: 207574
* Continue slp vectorization even the BB already has vectorized store ↵Yi Jiang2014-04-291-0/+31
| | | | | | radar://16641956 llvm-svn: 207572
* Add Simple return instruction to Mips fast-iselReed Kotler2014-04-291-0/+9
| | | | | | | | | | Reviewers: dsanders Reviewed by: dsanders Differential Revision: http://reviews.llvm.org/D3430 llvm-svn: 207565
* [ARM64] Disable regression tests for the old JIT.Tilmann Scheller2014-04-291-3/+4
| | | | | | Since the ARM64 backend doesn't implement support for the old JIT those tests are failing when the regression tests are run on an AArch64 host. llvm-svn: 207530
* [mips][msa] Use CHECK-LABEL in basic_operations*.llDaniel Sanders2014-04-292-42/+42
| | | | | | Differential Revision: http://reviews.llvm.org/D3536 llvm-svn: 207529
* Parse and create GOT_PREL relocations.Joerg Sonnenberger2014-04-291-0/+6
| | | | llvm-svn: 207526
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