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* AVX-512: Added FMA instructions, intrinsics an tests for KNL and SKX targetsElena Demikhovsky2014-12-232-0/+456
| | | | | | | | by Asaf Badouh http://reviews.llvm.org/D6456 llvm-svn: 224764
* [PowerPC] Don't mark the return-address slot as immutableHal Finkel2014-12-231-0/+25
| | | | | | | | | | | | | It is tempting to mark the fixed stack slot used to store the return address as immutable when lowering @llvm.returnaddress(i32 0). Unfortunately, within the function, it is not completely immutable: it is written during the function prologue. When using post-RA instruction scheduling, the prologue instructions are available for scheduling, and we're not free to interchange the order of a particular store in the prologue with loads from that stack location. Fixes PR21976. llvm-svn: 224761
* AVX-512: BLENDM - fixed encoding of the broadcast versionElena Demikhovsky2014-12-233-1/+345
| | | | | | Added more intrinsics and encoding tests. llvm-svn: 224760
* [DagCombine] Improve DAGCombiner BUILD_VECTOR when it has two sources of ↵Michael Kuperstein2014-12-231-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | elements This partially fixes PR21943. For AVX, we go from: vmovq (%rsi), %xmm0 vmovq (%rdi), %xmm1 vpermilps $-27, %xmm1, %xmm2 ## xmm2 = xmm1[1,1,2,3] vinsertps $16, %xmm2, %xmm1, %xmm1 ## xmm1 = xmm1[0],xmm2[0],xmm1[2,3] vinsertps $32, %xmm0, %xmm1, %xmm1 ## xmm1 = xmm1[0,1],xmm0[0],xmm1[3] vpermilps $-27, %xmm0, %xmm0 ## xmm0 = xmm0[1,1,2,3] vinsertps $48, %xmm0, %xmm1, %xmm0 ## xmm0 = xmm1[0,1,2],xmm0[0] To the expected: vmovq (%rdi), %xmm0 vmovhpd (%rsi), %xmm0, %xmm0 retq Fixing this for AVX2 is still open. Differential Revision: http://reviews.llvm.org/D6749 llvm-svn: 224759
* [PowerPC] Don't attempt a 64-bit pow2 division on PPC32Hal Finkel2014-12-231-0/+9
| | | | | | | | | | In r224033, in moving the signed power-of-2 division expansion into BuildSDIVPow2, I accidentally made it possible to attempt the lowering for a 64-bit division on PPC32. This later asserts. Fixes PR21928. llvm-svn: 224758
* [SimplifyCFG] Revise common code sinkingMichael Liao2014-12-231-2/+32
| | | | | | | | | | - Fix the case where more than 1 common instructions derived from the same operand cannot be sunk. When a pair of value has more than 1 derived values in both branches, only 1 derived value could be sunk. - Replace BB1 -> (BB2, PN) map with joint value map, i.e. map of (BB1, BB2) -> PN, which is more accurate to track common ops. llvm-svn: 224757
* [ARM] Don't break alignment when combining base updates into load/stores.Ahmed Bougacha2014-12-233-24/+105
| | | | | | | | | | | | | | | | | | r223862/r224203 tried to also combine base-updating load/stores. There was a mistake there: the alignment was added as is as an operand to the ARMISD::VLD/VST node. However, the VLD/VST selection logic doesn't care about less-than-standard alignment attributes. For example, no matter the alignment of a v2i64 load (say 1), SelectVLD picks VLD1q64 (because of the memory type). But VLD1q64 ("vld1.64 {dXX, dYY}") is 8-aligned, per ARMARMv7a 3.2.1. For the 1-aligned load, what we really want is VLD1q8. This commit introduces bitcasts if necessary, and changes the vld/vst type to one whose standard alignment matches the original load/store alignment. Differential Revision: http://reviews.llvm.org/D6759 llvm-svn: 224754
* Revert r224739: Debug info: Teach SROA how to update debug info forChandler Carruth2014-12-233-203/+4
| | | | | | | | | | | fragmented variables. This caused codegen to start crashing when we built somewhat large programs with debug info and optimizations. 'check-msan' hit in, and I suspect a bootstrap would as well. I mailed a test case to the review thread. llvm-svn: 224750
* X86: Don't over-align combined loads.Jim Grosbach2014-12-231-0/+35
| | | | | | | | | | | When combining consecutive loads+inserts into a single vector load, we should keep the alignment of the base load. Doing otherwise can, and does, lead to using overly aligned instructions. In the included test case, for example, using a 32-byte vmovaps on a 16-byte aligned value. Oops. rdar://19190968 llvm-svn: 224746
* Make musttail more robust for vector types on x86Reid Kleckner2014-12-222-0/+116
| | | | | | | | | | | | | | | | Previously I tried to plug musttail into the existing vararg lowering code. That turned out to be a mistake, because non-vararg calls use significantly different register lowering, even on x86. For example, AVX vectors are usually passed in registers to normal functions and memory to vararg functions. Now musttail uses a completely separate lowering. Hopefully this can be used as the basis for non-x86 perfect forwarding. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D6156 llvm-svn: 224745
* Thumb1 frame lowering: Mark CFI instructions with the FrameSetup flag.Adrian Prantl2014-12-221-1/+2
| | | | | | | | | | | | | Followup to r224294: ARM/AArch64: Attach the FrameSetup MIFlag to CFI instructions. Debug info marks the first instruction without the FrameSetup flag as being the end of the function prologue. Any CFI instructions in the middle of the function prologue would cause debug info to end the prologue too early and worse, attach the line number of the CFI instruction, which incidentally is often 0. llvm-svn: 224743
* [LCSSA] Handle PHI insertion in disjoint loopsBruno Cardoso Lopes2014-12-221-4/+36
| | | | | | | | | | | | | | | | | | | | Take two disjoint Loops L1 and L2. LoopSimplify fails to simplify some loops (e.g. when indirect branches are involved). In such situations, it can happen that an exit for L1 is the header of L2. Thus, when we create PHIs in one of such exits we are also inserting PHIs in L2 header. This could break LCSSA form for L2 because these inserted PHIs can also have uses in L2 exits, which are never handled in the current implementation. Provide a fix for this corner case and test that we don't assert/crash on that. Differential Revision: http://reviews.llvm.org/D6624 rdar://problem/19166231 llvm-svn: 224740
* Debug info: Teach SROA how to update debug info for fragmented variables.Adrian Prantl2014-12-223-4/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to generate debug info for extremely advanced code such as typedef struct { long int a; int b;} S; int foo(S s) { return s.b; } which at -O1 on x86_64 is codegen'd into define i32 @foo(i64 %s.coerce0, i32 %s.coerce1) #0 { ret i32 %s.coerce1, !dbg !24 } with this patch we emit the following debug info for this TAG_formal_parameter [3] AT_location( 0x00000000 0x0000000000000000 - 0x0000000000000006: rdi, piece 0x00000008, rsi, piece 0x00000004 0x0000000000000006 - 0x0000000000000008: rdi, piece 0x00000008, rax, piece 0x00000004 ) AT_name( "s" ) AT_decl_file( "/Volumes/Data/llvm/_build.ninja.release/test.c" ) Thanks to chandlerc, dblaikie, and echristo for their feedback on all previous iterations of this patch! llvm-svn: 224739
* Fix Windows unwind info for functions in sections other than .textReid Kleckner2014-12-221-2/+72
| | | | | | | | | | | Previously we assumed the section name had the form .text$foo, which is what we used to do for inline functions. If the dollar wasn't present, we'd put unwind data in the .pdata and .xdata sections for the main .text section, which is incorrect. Fixes PR22001. llvm-svn: 224738
* [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.Colin LeMahieu2014-12-222-2/+14
| | | | llvm-svn: 224735
* [Hexagon] Adding classes and load unsigned byte instruction, updating usages.Colin LeMahieu2014-12-221-0/+14
| | | | llvm-svn: 224730
* [x86] Add vector @llvm.ctpop intrinsic custom loweringBruno Cardoso Lopes2014-12-221-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when ctpop is supported for scalar types, the expansion of @llvm.ctpop.vXiY uses vector element extractions, insertions and individual calls to @llvm.ctpop.iY. When not, expansion with bit-math operations is used for the scalar calls. Local haswell measurements show that we can improve vector @llvm.ctpop.vXiY expansion in some cases by using a using a vector parallel bit twiddling approach, based on: v = v - ((v >> 1) & 0x55555555); v = (v & 0x33333333) + ((v >> 2) & 0x33333333); v = ((v + (v >> 4) & 0xF0F0F0F) v = v + (v >> 8) v = v + (v >> 16) v = v & 0x0000003F (from http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel) When scalar ctpop isn't supported, the approach above performs better for v2i64, v4i32, v4i64 and v8i32 (see numbers below). And even when scalar ctpop is supported, this approach performs ~2x better for v8i32. Here, x86_64 implies -march=corei7-avx without ctpop and x86_64h includes ctpop support with -march=core-avx2. == [x86_64h - new] v8i32: 0.661685 v4i32: 0.514678 v4i64: 0.652009 v2i64: 0.324289 == [x86_64h - old] v8i32: 1.29578 v4i32: 0.528807 v4i64: 0.65981 v2i64: 0.330707 == [x86_64 - new] v8i32: 1.003 v4i32: 0.656273 v4i64: 1.11711 v2i64: 0.754064 == [x86_64 - old] v8i32: 2.34886 v4i32: 1.72053 v4i64: 1.41086 v2i64: 1.0244 More work for other vector types will come next. llvm-svn: 224725
* [CodeGenPrepare] Handle properly the promotion of operands when this does notQuentin Colombet2014-12-221-0/+25
| | | | | | | | | generate instructions. Fixes PR21978. Related to <rdar://problem/18310086> llvm-svn: 224717
* AVX-512: Added all forms of BLENDM instructions,Elena Demikhovsky2014-12-223-2/+301
| | | | | | intrinsics, encoding tests for AVX-512F and skx instructions. llvm-svn: 224707
* Lower multiply-negate operation to mneg on AArch64Karthik Bhat2014-12-221-0/+15
| | | | | | | | | | | This patch pattern matches code such as- neg w8, w8 mul w8, w9, w8 to mneg w8, w8, w9 Review: http://reviews.llvm.org/D6754 llvm-svn: 224706
* Convert a few tests to FileCheck. NFC.Rafael Espindola2014-12-224-14/+38
| | | | llvm-svn: 224705
* Enable (sext x) == C --> x == (trunc C) combineMatt Arsenault2014-12-213-7/+542
| | | | | | | | | Extend the existing code which handles this for zext. This makes this more useful for targets with ZeroOrNegativeOne BooleanContent and obsoletes a custom combine SI uses for i1 setcc (sext(i1), 0, setne) since the constant will now be shrunk to i1. llvm-svn: 224691
* ARM: further improve deprecated diagnosis (LDM)Saleem Abdulrasool2014-12-201-5/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM ARM states: LDM/LDMIA/LDMFD: The SP can be in the list. However, ARM deprecates using these instructions with SP in the list. ARM deprecates using these instructions with both the LR and the PC in the list. LDMDA/LDMFA/LDMDB/LDMEA/LDMIB/LDMED: The SP can be in the list. However, instructions that include the SP in the list are deprecated. Instructions that include both the LR and the PC in the list are deprecated. POP: The SP can only be in the list before ARMv7. ARM deprecates any use of ARM instructions that include the SP, and the value of the SP after such an instruction is UNKNOWN. ARM deprecates the use of this instruction with both the LR and the PC in the list. Attempt to diagnose use of deprecated forms of these instructions. This mirrors the previous changes to diagnose use of the deprecated forms of STM in ARM mode. llvm-svn: 224682
* This should have been part of r224676.David Majnemer2014-12-201-2/+2
| | | | llvm-svn: 224677
* InstCombine: Squash an icmp+select into bitwise arithmeticDavid Majnemer2014-12-201-0/+33
| | | | | | | | | (X & INT_MIN) == 0 ? X ^ INT_MIN : X into X | INT_MIN (X & INT_MIN) != 0 ? X ^ INT_MIN : X into X & INT_MAX This fixes PR21993. llvm-svn: 224676
* InstSimplify: Optimize away pointless comparisonsDavid Majnemer2014-12-201-0/+76
| | | | | | | | | (X & INT_MIN) ? X & INT_MAX : X into X & INT_MAX (X & INT_MIN) ? X : X & INT_MAX into X (X & INT_MIN) ? X | INT_MIN : X into X (X & INT_MIN) ? X : X | INT_MIN into X | INT_MIN llvm-svn: 224669
* [x86] Change the test added in r223774 to first check the spelling ofChandler Carruth2014-12-201-26/+33
| | | | | | | | | | | | | | | the error message for a bogus processor, and then look specifically for that error message using FileCheck. I actually tried to write the test this way at first, but drew a blank on how to ensure the error message stayed in sync (oops). Now that I've recalled how to do that, this is clearly better. It also fixes an issue with a malloc implementation that actually prints to stderr in all cases, which was causing problems for some builders it seems. llvm-svn: 224665
* Masked load and store codegen - fixed 128-bit vectorsElena Demikhovsky2014-12-191-8/+78
| | | | | | | The codegen failed on 128-bit types on AVX2. I added patterns and in td files and tests. llvm-svn: 224647
* R600/SI: Only form min/max with 1 use.Matt Arsenault2014-12-193-0/+69
| | | | | | | If the condition is used for something else, this increases the number of instructions. llvm-svn: 224646
* Add printing the LC_ROUTINES load commands with llvm-objdump’s ↵Kevin Enderby2014-12-192-0/+14
| | | | | | -private-headers. llvm-svn: 224627
* Add the ExceptionHandling::MSVC enumerationReid Kleckner2014-12-194-4/+4
| | | | | | | | | | | | | | | It is intended to be used for a family of personality functions that have similar IR preparation requirements. Typically when interoperating with MSVC personality functions, bits of functionality need to be outlined from the main function into helper functions. There is also usually more than one landing pad per invoke, which does not match the LLVM IR landingpad representation. None of this is implemented yet. This change just adds a new enum that is active for *-windows-msvc and delegates to the EH removal preparation pass. No functionality change for other targets. llvm-svn: 224625
* Model sqrtss as a binary operation with one source operand tied to the ↵Sanjay Patel2014-12-191-5/+38
| | | | | | | | | | | destination (PR14221) This is a continuation of r167064 ( http://llvm.org/viewvc/llvm-project?view=revision&revision=167064 ). That patch started to fix PR14221 ( http://llvm.org/bugs/show_bug.cgi?id=14221 ), but it was not completed. Differential Revision: http://reviews.llvm.org/D6330 llvm-svn: 224624
* R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operandTom Stellard2014-12-191-0/+39
| | | | | | | | mubuf instructions now define the soffset field using the SCSrc_32 register class which indicates that only SGPRs and inline constants are allowed. llvm-svn: 224622
* Add printing the LC_SUB_CLIENT load command with llvm-objdump’s ↵Kevin Enderby2014-12-192-0/+7
| | | | | | -private-headers. llvm-svn: 224616
* CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.Peter Collingbourne2014-12-191-0/+19
| | | | llvm-svn: 224615
* [Hexagon] Removing old variants of instructions and updating references.Colin LeMahieu2014-12-191-0/+2
| | | | llvm-svn: 224612
* merge consecutive stores of extracted vector elementsSanjay Patel2014-12-191-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a path to DAGCombiner::MergeConsecutiveStores() to combine multiple scalar stores when the store operands are extracted vector elements. This is a partial fix for PR21711 ( http://llvm.org/bugs/show_bug.cgi?id=21711 ). For the new test case, codegen improves from: vmovss %xmm0, (%rdi) vextractps $1, %xmm0, 4(%rdi) vextractps $2, %xmm0, 8(%rdi) vextractps $3, %xmm0, 12(%rdi) vextractf128 $1, %ymm0, %xmm0 vmovss %xmm0, 16(%rdi) vextractps $1, %xmm0, 20(%rdi) vextractps $2, %xmm0, 24(%rdi) vextractps $3, %xmm0, 28(%rdi) vzeroupper retq To: vmovups %ymm0, (%rdi) vzeroupper retq Patch reviewed by Nadav Rotem. Differential Revision: http://reviews.llvm.org/D6698 llvm-svn: 224611
* [Hexagon] Adding bit extraction and table indexing instructions.Colin LeMahieu2014-12-191-0/+16
| | | | llvm-svn: 224610
* [Hexagon] Adding bit insertion instructions.Colin LeMahieu2014-12-191-0/+8
| | | | llvm-svn: 224609
* [Hexagon] Adding more xtype shift instructions.Colin LeMahieu2014-12-192-0/+22
| | | | llvm-svn: 224608
* Add printing the LC_SUB_LIBRARY load command with llvm-objdump’s ↵Kevin Enderby2014-12-192-0/+7
| | | | | | -private-headers. llvm-svn: 224607
* [Hexagon] Adding xtype shift instructions.Colin LeMahieu2014-12-192-0/+132
| | | | llvm-svn: 224604
* [Hexagon] Adding transfers to and from control registers.Colin LeMahieu2014-12-191-1/+5
| | | | llvm-svn: 224599
* Reapply: [InstCombine] Fix visitSwitchInst to use right operand types for ↵Bruno Cardoso Lopes2014-12-191-0/+30
| | | | | | | | | | | | | | | | | | sub cstexpr The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. Also, fix code to also return the modified switch when only the truncation is performed. This fixes an assertion crash. Differential Revision: http://reviews.llvm.org/D6644 rdar://problem/19191835 llvm-svn: 224588
* use -0.0 when creating an fneg instructionSanjay Patel2014-12-191-1/+1
| | | | | | | | | | | | | | | | | | | Backends recognize (-0.0 - X) as the canonical form for fneg and produce better code. Eg, ppc64 with 0.0: lis r2, ha16(LCPI0_0) lfs f0, lo16(LCPI0_0)(r2) fsubs f1, f0, f1 blr vs. -0.0: fneg f1, f1 blr Differential Revision: http://reviews.llvm.org/D6723 llvm-svn: 224583
* Revert "[InstCombine] Fix visitSwitchInst to use right operand types for sub ↵Bruno Cardoso Lopes2014-12-191-30/+0
| | | | | | | | | | | | | cstexpr" Reverts commit r224574 to appease buildbots: The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. This fixes an assertion crash. llvm-svn: 224576
* [InstCombine] Fix visitSwitchInst to use right operand types for sub cstexprBruno Cardoso Lopes2014-12-191-0/+30
| | | | | | | | | | | | | The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. This fixes an assertion crash. Differential Revision: http://reviews.llvm.org/D6644 rdar://problem/19191835 llvm-svn: 224574
* [Object] Don't crash on empty export lists.Juergen Ributzka2014-12-192-0/+4
| | | | | | | | | | | | Summary: This fixes the exports iterator if the export list is empty. Reviewers: Bigcheese, kledzik Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6732 llvm-svn: 224563
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-191-0/+20
| | | | llvm-svn: 224556
* ConstantFold: Shifting undef by zero results in undefDavid Majnemer2014-12-181-0/+21
| | | | llvm-svn: 224553
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