summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* Revert r315992 because of a found miscompilation failureNikolai Bozhenov2017-10-191-10/+10
| | | | llvm-svn: 316164
* [X86] Replace custom scalar integer absolute matching with ISD::ABS lowering.Simon Pilgrim2017-10-191-5/+2
| | | | | | | | | | | | x86 has its own copy of integer absolute pattern matching to combine directly to a SUB+CMOV. This patch removes the x86 combine and adds custom lowering support for ISD::ABS instead, allowing us to use the DAGCombiner version. Additional test cases are already covered by iabs.ll (rL315706 and rL315711). Differential Revision: https://reviews.llvm.org/D38895 llvm-svn: 316162
* [X86] Add scalar (abs (abs x)) -> (abs x) combine test.Simon Pilgrim2017-10-191-0/+19
| | | | | | Before landing D38895 llvm-svn: 316160
* [ARM GlobalISel] Fix liveins in test. NFCDiana Picus2017-10-191-2/+2
| | | | llvm-svn: 316155
* [ARM GlobalISel] Remove redundant testsDiana Picus2017-10-192-548/+0
| | | | | | | These test cases don't really add anything that isn't covered by other tests as well, so we can safely remove them. llvm-svn: 316154
* Fix buffer overflow.Rafael Espindola2017-10-192-0/+3
| | | | | | We were reading past the end of the buffer. llvm-svn: 316143
* GISel: Canonicalize select tests using update_mir_test_checksJustin Bogner2017-10-1843-2349/+2519
| | | | | | | | This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
* AArch64/GISel: Modernize the localizer testJustin Bogner2017-10-181-259/+203
| | | | llvm-svn: 316138
* Canonicalize a large number of mir tests using update_mir_test_checksJustin Bogner2017-10-1852-1494/+1358
| | | | | | | | | | This converts a large and somewhat arbitrary set of tests to use update_mir_test_checks. I ran the script on all of the tests I expect to need to modify for an upcoming mir syntax change and kept the ones that obviously didn't change the tests in ways that might make it harder to understand. llvm-svn: 316137
* Revert "[ScalarEvolution] Handling for ICmp occuring in the evolution chain."Sanjoy Das2017-10-181-19/+0
| | | | | | | This reverts commit r316054. There was some confusion over the review process: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20171016/495884.html llvm-svn: 316129
* Fix lit.site.cfg.py.in after rL316123Sam Clegg2017-10-181-1/+1
| | | | llvm-svn: 316126
* [AVR] Fix the select_mbb_placement_bug.ll testDylan McKay2017-10-181-3/+3
| | | | llvm-svn: 316124
* Don't set static-libs test feature when using LLVM_LINK_LLVM_DYLIBSam Clegg2017-10-183-3/+6
| | | | | | | | | This was causing execname-options.ll to fail on the wasm waterfall. Differential Revision: https://reviews.llvm.org/D39022 llvm-svn: 316123
* [llvm-cov] Suppress sub-line highlights in simple casesVedant Kumar2017-10-182-15/+3
| | | | | | | | | | llvm-cov tends to highlight too many regions because its policy is to highlight all region entry segments. This can look confusing to users: not all region entry segments are interesting and deserve highlighting. Emitting these highlights only when the region count differs from the line count is a more user-friendly policy. llvm-svn: 316109
* [llvm-cov] Highlight gaps in consecutive uncovered regionsVedant Kumar2017-10-181-0/+1
| | | | | | | llvm-cov typically doesn't highlight gap segments, but it should if the gap occurs after an uncovered region in order to preserve continuity. llvm-svn: 316107
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-18103-131/+132
| | | | | | | | | | | | | | | | | | | | | | This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
* AMDGPU: Rename MaxFlatWorkgroupSize to MaxFlatWorkGroupSize for consistencyKonstantin Zhuravlyov2017-10-183-7/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D38957 llvm-svn: 316097
* [RISCV] Bugfix createRISCVELFObjectWriterAlex Bradbury2017-10-181-0/+42
| | | | | | | r315275 set the IsLittleEndian parameter incorrectly. This patch corrects this, and adds a test to ensure such mistakes will be caught in the future. llvm-svn: 316091
* AArch64/GISel: Fix a couple of tests that were testing the wrong thingJustin Bogner2017-10-184-47/+65
| | | | | | | | Fix a couple of tests that were extending the wrong vreg, and regenerate their checks with update_mir_test_checks. This looks like it was a copy-paste or test update error. llvm-svn: 316087
* [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM modeAndre Vieira2017-10-182-0/+85
| | | | | | Differential Revision: https://reviews.llvm.org/D38347 llvm-svn: 316085
* [mips] Fix analyzeBranch to handle debug dataSimon Dardis2017-10-181-0/+90
| | | | | | | | | | | | | | | | | | | | | In the case where there was a conditional branch followed by a unconditional branch with debug instruction separating them, MipsInstrInfo::analyzeBranch would not skip past debug instruction when searching for the second branch which give erroneous results about the control flow of the block. This could lead to the branch folder to merge the non-fall through case into it's predecessor, leaving the conditional branch with a dangling basic block operand. This resolves PR34975. Thanks to Alexander Richardson for reporting the issue! Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39003 llvm-svn: 316084
* [mips] Move test to correct directory. NFCISimon Dardis2017-10-181-0/+0
| | | | llvm-svn: 316081
* Adding new test forMichael Zuckerman2017-10-181-0/+15
| | | | | | | | | | bug fix 316067 https://bugs.llvm.org/show_bug.cgi?id=34978 This test checks that the x86-interleaved ends without any assertion. Change-Id: I1e970482a4d0404516cbc85517fc091bb21c35a8 llvm-svn: 316080
* [AVX512][AVX2]Cost calculation for interleave load/store patterns ↵Michael Zuckerman2017-10-183-10/+10
| | | | | | | | | | | | | | | | | | | {v8i8,v16i8,v32i8,v64i8} This patch adds accurate instructions cost. The formula presents two cases(stride 3 and stride 4) and calculates the cost according to the VF and stride. Reviewers: 1. delena 2. Farhana 3. zvi 4. dorit 5. Ayal Differential Revision: https://reviews.llvm.org/D38762 Change-Id: If4cfbd4ac0e63694e8144cb78c7fa34850647ff7 llvm-svn: 316072
* [PowerPC] Use helper functions to check sign-/zero-extended valueHiroshi Inoue2017-10-181-0/+21
| | | | | | | | | | | Helper functions to identify sign- and zero-extending machine instruction is introduced in rL315888. This patch makes PPCInstrInfo::optimizeCompareInstr use the helper functions. It simplifies the code and also makes possible more optimizations since the helper can do more analysis than the original check code; I observed about 5000 more compare instructions are eliminated while building LLVM. Also, this patch fixes a bug in helpers on ANDIo instruction handling due to the order of checks. This bug causes a failure in an existing test case for optimizeCompareInstr. Differential Revision: https://reviews.llvm.org/D38988 llvm-svn: 316071
* Improve lookThroughCast function.Nikolai Bozhenov2017-10-181-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When we have the following case: %cond = cmp iN %x, CmpConst %tr = trunc iN %x to iK %narrowsel = select i1 %cond, iK %t, iK C We could possibly match only min/max pattern after looking through cast. So it is more profitable if widened C constant will be equal CmpConst. That is why just set widened C constant equal to CmpConst, because there is a further check in this function that trunc CmpConst == C. Also description for lookTroughCast function was added. Reviewers: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38536 Patch by: Artur Gainullin <artur.gainullin@intel.com> llvm-svn: 316070
* [ScalarEvolution] Handling for ICmp occuring in the evolution chain.Jatin Bhateja2017-10-181-0/+19
| | | | | | | | | | | | | | | | | | | | | | Summary: If a compare instruction is same or inverse of the compare in the branch of the loop latch, then return a constant evolution node. Currently scope of evaluation is limited to SCEV computation for PHI nodes. This shall facilitate computations of loop exit counts in cases where compare appears in the evolution chain of induction variables. Will fix PR 34538 Reviewers: sanjoy, hfinkel, junryoungju Reviewed By: junryoungju Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D38494 llvm-svn: 316054
* Verifier: Ignore CUs pulled in by ODR-uniqued types.Adrian Prantl2017-10-182-0/+200
| | | | | | | | | | | | | | | When more than one Module is imported into the same context, such as during an LTO build before linking the modules, ODR type uniquing may cause types to point to a different CU. This check does not make sense in this case. This fixes the error reported in PR34944. https://bugs.llvm.org/show_bug.cgi?id=34944 rdar://problem/34940685 This reapplies a cleaner implementation of r316049. llvm-svn: 316052
* Revert "Verifier: Ignore CUs pulled in by ODR-uniqued types."Adrian Prantl2017-10-182-200/+0
| | | | | | This reverts commit r316049. llvm-svn: 316050
* Verifier: Ignore CUs pulled in by ODR-uniqued types.Adrian Prantl2017-10-182-0/+200
| | | | | | | | | | | | | When more than one Module is imported into the same context, such as during an LTO build before linking the modules, ODR type uniquing may cause types to point to a different CU. This check does not make sense in this case. This fixes the error reported in PR34944. https://bugs.llvm.org/show_bug.cgi?id=34944 rdar://problem/34940685 llvm-svn: 316049
* AMDGPU : Fix an error for the llvm.cttz implementation.Wei Ding2017-10-171-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D39014 llvm-svn: 316037
* AArch64: account for possible frame index operand in compares.Tim Northover2017-10-171-0/+19
| | | | | | | | | If the address of a local is used in a comparison, AArch64 can fold the address-calculation into the comparison via "adds". Unfortunately, a couple of places (both hit in this one test) are not ready to deal with that yet and just assume the first source operand is a register. llvm-svn: 316035
* [X86][SSE] Tests packuswb/truncation codegen from PR34773Simon Pilgrim2017-10-171-0/+120
| | | | llvm-svn: 316033
* AMDGPU: Start generating metadata for MaxFlatWorkGroupSizeKonstantin Zhuravlyov2017-10-173-11/+27
| | | | | | Differential Revision: https://reviews.llvm.org/D38958 llvm-svn: 316024
* [ARM, AArch64] adjust tests trying to maintain their objective; NFCSanjay Patel2017-10-172-2/+2
| | | | | | | A smarter compiler will see that these might be better without a jump table if we're just using the constant values of the switch. llvm-svn: 316012
* [SimplifyCFG] add test for part of PR34471 (switch squashing); NFCSanjay Patel2017-10-171-0/+43
| | | | llvm-svn: 316008
* [SimplifyCFG] update test to use auto-generated FileCheck asserts; NFCSanjay Patel2017-10-171-7/+14
| | | | llvm-svn: 316006
* [X86][Broadwell] Added the broadwell cpu to the scheduling regression ↵Gadi Haber2017-10-1719-8/+4607
| | | | | | | | | | | | | tests.<NFC> NFC. Added the Broadwell cpu and the BROADWELL prefix to all the scheduling regression tests, as part of prepartion for a larger commit of adding all Broadwell scheduiling. Reviewers: RKSimon, zvi, aaboud Differential Revision: https://reviews.llvm.org/D38994 Change-Id: I54bc9065168844c107b1729fcdc1d311ce3ea0a9 llvm-svn: 315998
* Improve clamp recognition in ValueTracking.Nikolai Bozhenov2017-10-171-10/+10
| | | | | | | | | | | | | | | | | | | Summary: ValueTracking was recognizing not all variations of clamp. Swapping of true value and false value of select was added to fix this problem. This change breaks the canonical form of cmp inside the matchMinMax function, that is why additional checks for compare predicates is needed. Added corresponding test cases. Reviewers: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38531 Patch by: Artur Gainullin <artur.gainullin@intel.com> llvm-svn: 315992
* Fix implicit null check with negative offsetYichao Yu2017-10-172-2/+55
| | | | | | | | | | | | | | | | | | | | Summary: It seems that negative offset was accidentally allowed in D17967. AFAICT small negative offset should be valid (always raise segfault) on all archs that I'm aware of (especially x86, which is the only one with this optimization enabled) and such case can be useful when loading hiden metadata from an object. However, like the positive side, it should only be done within a certain limit. For now, use the same limit on the positive side for the negative side. A separate option can be added if needs appear. Reviewers: mcrosier, skatkov Reviewed By: skatkov Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D38925 llvm-svn: 315991
* [X86][Skylake] fixed/updated regression test mmx-schedule.ll which failed ↵Gadi Haber2017-10-171-274/+274
| | | | | | | after r315978. Change-Id: I60cd7e03ea6c3d9a3dc661a882458e83feca66e3 llvm-svn: 315985
* More tests with x86 prefixes which work after rL315899 commitAndrew V. Tischenko2017-10-172-0/+125
| | | | llvm-svn: 315983
* [X86][SKL] Updated scheduling information for the SkylakeClient targetGadi Haber2017-10-1718-1462/+1564
| | | | | | | | | | | | | | Updated the scheduling information for the SkylakeClient target with the following changes: 1. regrouped the instructions after adding load and store latencies. 2. regrouped the instructions after adding identified missing ports in several groups. The changes were made after revisiting the latencies impact of all the load and store uOps. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D38727 Change-Id: I778a308cc11e490e8fa5e27e2047412a1dca029f llvm-svn: 315978
* Remove a test after revert of rL315440Max Kazantsev2017-10-171-146/+0
| | | | llvm-svn: 315977
* [NFC] Add test from bug 34937Max Kazantsev2017-10-171-0/+32
| | | | llvm-svn: 315976
* Revert 315440 on behalf of mkazantsevPhilip Reames2017-10-171-28/+0
| | | | | | | | | | | This patch reverts rL315440 because of the bug described at https://bugs.llvm.org/show_bug.cgi?id=34937 The fix for the bug is on review as D38944, but not yet ready. Given this is a regression reverting until a fix is ready is called for. Max would have done the revert himself, but is having trouble doing a build of fresh LLVM for some reason. I did the build and test to ensure the revert worked as expected on his behalf. llvm-svn: 315974
* [globalisel][tablegen] Add a GIM_CheckIsSameOperand test where OtherInsnID ↵Daniel Sanders2017-10-171-0/+61
| | | | | | and OtherOpIdx differ llvm-svn: 315972
* [X86] Add masked palignr tests to vector-shuffle-masked.llCraig Topper2017-10-171-0/+75
| | | | llvm-svn: 315971
* [X86] Add AVX512BW to the vector-shuffle-masked test to prepare for an ↵Craig Topper2017-10-171-133/+133
| | | | | | upcoming commit. llvm-svn: 315970
* [ExecutionEngine] Correct the size of a write in a COFF i386 relocationShoaib Meenai2017-10-171-7/+11
| | | | | | | | | | | We want to be writing a 32bit value, so we should be writing 4 bytes instead of 2. Patch by Alex Langford <apl@fb.com>. Differential Revision: https://reviews.llvm.org/D38872 llvm-svn: 315964
OpenPOWER on IntegriCloud