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* [PowerPC] No CTR loop if the candidate exiting block is in a different loopNemanja Ivanovic2018-05-021-0/+67
| | | | | | | | | | | | | | | | The CTR loops pass will insert the decrementing branch instruction in an exiting block for the loop being transformed. However if that block is part of another loop as well (whether a nested loop or with irreducible CFG), it is not valid to use that exiting block. In fact, if the loop hass irreducible CFG, we don't bother analyzing it and we just bail on the transformation. In practice, this doesn't lead to a noticeable reduction in the number of loops transformed by this pass. Fixes https://bugs.llvm.org/show_bug.cgi?id=37229 Differential Revision: https://reviews.llvm.org/D46162 llvm-svn: 331410
* [GCOV] Emit the writeout function as nested loops of global data.Chandler Carruth2018-05-021-3/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Prior to this change, LLVM would in some cases emit *massive* writeout functions with many 10s of 1000s of function calls in straight-line code. This is a very wasteful way to represent what are fundamentally loops and creates a number of scalability issues. Among other things, register allocating these calls is extremely expensive. While D46127 makes this less severe, we'll still run into scaling issues with this eventually. If not in the compile time, just from the code size. Now the pass builds up global data structures modeling the inputs to these functions, and simply loops over the data structures calling the relevant functions with those values. This ensures that the code size is a fixed and only data size grows with larger amounts of coverage data. A trivial change to IRBuilder is included to make it easier to build the constants that make up the global data. Reviewers: wmi, echristo Subscribers: sanjoy, mcrosier, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D46357 llvm-svn: 331407
* [llvm-rc] Default to writing the output next to the input, if no output is ↵Martin Storsjo2018-05-022-1/+6
| | | | | | | | | | specified This matches what rc.exe does if no output is specified. Differential Revision: https://reviews.llvm.org/D46239 llvm-svn: 331403
* [llvm-cvtres] Allow parameters preceded by '-' in addition to '/'Martin Storsjo2018-05-021-0/+4
| | | | | | | | The real cvtres.exe also allows parameters in either form. Differential Revision: https://reviews.llvm.org/D46358 llvm-svn: 331402
* [llvm-objcopy] Add --discard-all (-x) optionPaul Semel2018-05-021-0/+91
| | | | llvm-svn: 331400
* [llvm-objcopy] Add --weaken optionPaul Semel2018-05-021-0/+94
| | | | llvm-svn: 331397
* [GlobalISel][InstructionSelect] Refactoring out a getMatchTable virtual ↵Roman Tereshin2018-05-021-4/+9
| | | | | | | | | | | | | | | | | | | | | method + other small NFC's The main goal is to share getMatchTable between the Instruction Selector and the Testgen. The commit also contains some NFC only loosely related to refactoring out the getMatchTable, but strongly related to the initial Testgen patch (see https://reviews.llvm.org/D43962) Reviewers: dsanders, aemerson Reviewed By: dsanders Subscribers: rovka, kristof.beyls, llvm-commits, dsanders Differential Revision: https://reviews.llvm.org/D46096 llvm-svn: 331395
* [llvm-rc] Add rudimentary support for codepagesMartin Storsjo2018-05-025-0/+60
| | | | | | | | | | | | | | | | | | | | | | Only support UTF-8 (since LLVM contains UTF-8 parsing support already, and the code even does that already) and Windows-1252 (where most code points has the same value in unicode). Keep the existing default as only allowing ASCII input. Using the option type JoinedOrSeparate, since the real rc.exe handles options in this form, even if llvm-rc uses Separate for other similar existing options. Rename the struct SearchParams to WriterParams since it's now used for more than just include paths. Add a missing getResourceTypeName method to the BundleResource class, to fix error printing from within STRINGTABLE resources (used in tests). Differential Revision: https://reviews.llvm.org/D46238 llvm-svn: 331391
* [X86][SNB] Fix scheduling of MMX integer multiply instructions.Simon Pilgrim2018-05-025-24/+24
| | | | | | The entries were being bound to the wrong class. llvm-svn: 331388
* [X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM ↵Simon Pilgrim2018-05-024-134/+134
| | | | | | and YMM/ZMM scheduler classes llvm-svn: 331386
* [COFF, ARM64] Hook up a few remaining relocationsMartin Storsjo2018-05-021-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D46355 llvm-svn: 331384
* [AMDGPU] A trivial fix for a buildbot failure caused by "commit ↵Farhana Aleen2018-05-021-0/+39
| | | | | | | 224a839fcbbead221f872cd32a1dd0c308d37299". Author: FarhanaAleen llvm-svn: 331383
* [reassociate] Fix excessive revisits when processing long chains of ↵Daniel Sanders2018-05-021-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | reassociatable instructions. Summary: Some of our internal testing detected a major compile time regression which I've tracked down to: r278938 - Revert "Reassociate: Reprocess RedoInsts after each inst". It appears that processing long chains of reassociatable instructions causes non-linear (potentially exponential) growth in the number of times an instruction is revisited. For example, the included test revisits instructions 220 times in a 20-instruction test. It appears that r278938 reversed the order instructions were visited and that this is preventing scheduled revisits from being cancelled as a result of visiting the instructions naturally during normal processing. However, simply reversing the order also harmed the generated code. Upon closer inspection, it was discovered that revisits occurred in the opposite order to the first pass (Thanks to escha for spotting that). This patch makes the revisit order consistent with the first pass which allows more revisits to be cancelled. This does appear to have a small impact on the generated code in few cases but it significantly reduces compile-time. After this patch, our internal test that was most affected by the regression dropped from ~2 million revisits to ~4k resulting in Reassociate having 0.46% of the runtime it had before (99.54% improvement). Here's the summaries reported by lnt for the LLVM test-suite with --benchmarking-only: | metric | geomean before patch | geomean after patch | delta | | ----- | ----- | ----- | ----- | | compile time | 0.1956 | 0.1261 | -35.54% | | execution time | 0.3240 | 0.3237 | - | | code size | 7365.4459 | 7365.6079 | - | The results have a few wins and losses on compile-time, mostly in the +/- 2.5% range. There was one outlier though: | Performance Regressions - compile_time | Δ | Previous | Current | | MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 9.82% | 2.0473 | 2.2483 | Reviewers: javed.absar, dberlin Reviewed By: dberlin Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45734 llvm-svn: 331381
* [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler ↵Simon Pilgrim2018-05-024-281/+281
| | | | | | classes with more common default values llvm-svn: 331380
* Revert "[AMDGPU] performAddCombine should run after DAG is legalized."Farhana Aleen2018-05-021-39/+0
| | | | | | This reverts commit 6b97d2995566b4dddd6bf0d75579ff44501d4494. llvm-svn: 331371
* [AMDGPU] performAddCombine should run after DAG is legalized.Farhana Aleen2018-05-021-0/+39
| | | | | | | | | | | | | | | | Summary: performAddCombine should run after DAG is legalized; Otherwise generic optimization in the DAGCombiner can optimize an addcarry+trunc into an addcarry instruction with illegal types. Author: FarhanaAleen Reviewed By: rampitec Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D46337 llvm-svn: 331368
* [X86] Fix scheduling info for (V?)SQRTPDm on silvermont.Clement Courbet2018-05-021-2/+2
| | | | | | https://reviews.llvm.org/D46356 llvm-svn: 331356
* [AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.Sander de Smalen2018-05-024-0/+136
| | | | | | | | | | Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D46270 llvm-svn: 331352
* [TableGen] Don't quote variable name when printing !foreach.Simon Tatham2018-05-021-0/+3
| | | | | | | | | | | | | | | | | An input !foreach expression such as !foreach(a, lst, !add(a, 1)) would be re-emitted by llvm-tblgen -print-records with the first argument in quotes, giving !foreach("a", lst, !add(a, 1)), which isn't valid TableGen input syntax. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46352 llvm-svn: 331351
* [AArch64][SVE] Asm: Support for scatter ST1 store instructions.Sander de Smalen2018-05-028-0/+544
| | | | | | | | | | Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46248 llvm-svn: 331349
* Revert "[mips] Correct the predicates of sign extension instructions"Simon Dardis2018-05-029-40/+4
| | | | | | | | | I accidently committed this patch after asking for a review, but it has not been reviewed yet. This reverts r331346. llvm-svn: 331348
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-029-4/+40
| | | | | | And eliminate the duplication of those instructions for microMIPS32r6. llvm-svn: 331346
* [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 ↵Sander de Smalen2018-05-0216-0/+812
| | | | | | | | | | | | load/store instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D46269 llvm-svn: 331343
* [mips] Correct the predicates for shifts.Simon Dardis2018-05-0216-11/+495
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
* [X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default ↵Simon Pilgrim2018-05-022-23/+23
| | | | | | | | | | values Intel models were targeting x87 instead of packed sse. Also fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY. llvm-svn: 331340
* [AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector ↵Sander de Smalen2018-05-028-0/+476
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46250 llvm-svn: 331339
* Mark invariant.group.barrier as inaccessiblememonlyPiotr Padlewski2018-05-022-44/+126
| | | | | | | | | | | | | | | | It turned out that readonly argmemonly is not enough. store 42, %p %b = barrier(%p) store 43, %b the first store is dead, but because barrier was marked as reading argument memory, it was considered alive. With inaccessiblememonly it doesn't read the argument, but it also can't be CSEd. based on: https://reviews.llvm.org/D32006 llvm-svn: 331338
* [SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)Bjorn Pettersson2018-05-021-0/+169
| | | | | | | | | | | | | | | | | | | | | Summary: This is a follow up to rL331182. A PHI node can be split up into several MIR PHI nodes when being selected. When there is a dbg.value intrinsic that uses the result of such a PHI node we need to select several DBG_VALUE instructions, with fragment expressions, in order to do a correct selection. Reviewers: rnk, aprantl, vsk Reviewed By: vsk Subscribers: mattd, llvm-commits, JDevlieghere, aprantl, gbedwell, rnk Tags: #debug-info Differential Revision: https://reviews.llvm.org/D46329 llvm-svn: 331337
* [AMDGPU] Support horizontal vectorization.Farhana Aleen2018-05-012-0/+474
| | | | | | | | | | | | Author: FarhanaAleen Reviewed By: rampitec, arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D46213 llvm-svn: 331313
* [AggressiveInstCombine] convert a chain of 'or-shift' bits into masked compareSanjay Patel2018-05-012-36/+20
| | | | | | | | | | | | | | | | | | | | | and (or (lshr X, C), ...), 1 --> (X & C') != 0 I initially thought about implementing the minimal pattern in instcombine as mentioned here: https://bugs.llvm.org/show_bug.cgi?id=37098#c6 ...but we need to do better to catch the more general sequence from the motivating test (more than 2 bits in the compare). And a test-suite run with statistics showed that this pattern only happened 2 times currently. It would potentially happen more often if reassociation worked better (D45842), but it's probably still not too frequent? This is small enough that I didn't see a need to create a whole new class/file within AggressiveInstCombine. There are likely other relatively small matchers like what was discussed in D44266 that would slide under foldUnusualPatterns() (name suggestions welcome). We could potentially also consolidate matchers for ctpop, bswap, etc under here. Differential Revision: https://reviews.llvm.org/D45986 llvm-svn: 331311
* [AggressiveInstCombine] add more bitfield test patterns; NFCSanjay Patel2018-05-011-4/+50
| | | | | | | Add another baseline for D45986 and a pattern that won't be matched with that patch. llvm-svn: 331309
* [PhaseOrdering] add tests for bittest patterns from bitfields; NFCSanjay Patel2018-05-011-0/+152
| | | | | | | | | As mentioned in D45986, there's a potential ordering dependency between instcombine and aggressive-instcombine for detecting these, so I'm adding a few tests to confirm that the expected folds occur using -O3 (because aggressive-instcombine only runs at -O3 currently). llvm-svn: 331308
* [AArch64] Add more tests for 64-bit immediate lowering.Eli Friedman2018-05-011-51/+223
| | | | | | | | | | This adds a some more tests, and adds some notes to tests which are using a suboptimal lowering. The constants with suboptimal lowerings seem to be relatively rare in practice, but it might be a fun project to work on improvements. llvm-svn: 331304
* [DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)Vedant Kumar2018-05-012-8/+46
| | | | | | | | | | | | | | | | The logic for this combine is almost identical to the logic for a (sext (sextload x)) combine. This commit factors out the logic so it can be shared by both combines, and corrects the SDLoc assigned in the zext version of the combine. Prior to this patch, for the given test case, we would apply the location associated with the udiv instruction to instructions which perform the load. Part of: llvm.org/PR37262 llvm-svn: 331303
* [DAGCombiner] Fix SDLoc in a (sext (sextload x)) combine (3/N)Vedant Kumar2018-05-011-0/+38
| | | | | | | | | | | | Prior to this patch, for the given test case, we would apply the location associated with the sdiv instruction to instructions which perform the load. Part of: llvm.org/PR37262. Differential Revision: https://reviews.llvm.org/D46222 llvm-svn: 331302
* [DAGCombiner] Change the SDLoc on split extloads (2/N)Vedant Kumar2018-05-017-212/+211
| | | | | | | | | | | | | | | | | | | | | In DAGCombiner, we try to simplify this pattern: ([s|z]ext (load ...)) Conceptually, a new extload which is created while splitting the load should have the same debug location as the load. Making this change affects the IROrder of the new load, causing some test case churn. In practice, the new location is never different from the location of the [s|z]ext, at least not during check-llvm or a stage2 build. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46156 llvm-svn: 331301
* [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)Vedant Kumar2018-05-0116-204/+240
| | | | | | | | | | | | | | | | | | | | | Setting the right SDLoc on a newly-created zextload fixes a line table bug which resulted in non-linear stepping behavior. Several backend tests contained CHECK lines which relied on the IROrder inherited from the wrong SDLoc. This patch breaks that dependence where feasbile and regenerates test cases where not. In some cases, changing a node's IROrder may alter register allocation and spill behavior. This can affect performance. I have chosen not to prevent this by applying a "known good" IROrder to SDLocs, as this may hide a more general bug in the scheduler, or cause regressions on other test inputs. rdar://33755881, Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D45995 llvm-svn: 331300
* AMDGPU: Remove remnants of gfx901 (it was deprecated some time ago)Konstantin Zhuravlyov2018-05-012-2/+2
| | | | llvm-svn: 331298
* [X86] Split WriteFMul/WriteFDiv into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-7/+7
| | | | llvm-svn: 331293
* llvm-symbolizer: Handle function definitions nested within other functionsDavid Blaikie2018-05-012-0/+5
| | | | | | | | | | | | LLVM always puts function definition DIEs at the top level, but under some circumstances GCC does not (at least in this case with member functions of a function-local type). To ensure that doesn't appear as though the local type's member function is unduly inlined within the outer function - ensure the inline discovery DIE parent walk stops at the first DW_TAG_subprogram. llvm-svn: 331291
* Use no-op opt run to eliminate the difference in bb pred comment, per ↵Wei Mi2018-05-011-6/+3
| | | | | | chandler's suggestion. It is better than using sed on portability. llvm-svn: 331286
* AMDGPU: Add missing gfx904 testsKonstantin Zhuravlyov2018-05-012-0/+2
| | | | llvm-svn: 331284
* [LV] Move test/Transforms/LoopVectorize/pr23997.llDaniel Neilson2018-05-011-0/+0
| | | | | | | | | | | | | Summary: This fixes a build break with r331269. test/Transforms/LoopVectorize/pr23997.ll should be in: test/Transforms/LoopVectorize/X86/pr23997.ll llvm-svn: 331281
* Fix the sed command in test which doesn't work well on BSD.Wei Mi2018-05-011-3/+6
| | | | llvm-svn: 331280
* [WebAssembly] llvm-readobj: display symbols names in relocationsSam Clegg2018-05-015-52/+56
| | | | | | Differential Revision: https://reviews.llvm.org/D46296 llvm-svn: 331279
* [X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classesSimon Pilgrim2018-05-011-12/+12
| | | | | | Removes more WriteFAdd InstRW overrides llvm-svn: 331276
* [SLP] Add additional test for transposable binary operations with reuseMatthew Simpson2018-05-011-2/+44
| | | | llvm-svn: 331274
* [DAG] add test to show FMF mismatch between IR and DAG; NFCSanjay Patel2018-05-011-0/+32
| | | | | | | D45710 proposes to change this, but we have no test coverage for the first step in this process. llvm-svn: 331271
* [LV] Preserve inbounds on created GEPsDaniel Neilson2018-05-0111-251/+360
| | | | | | | | | | | | | | | | | | | Summary: This is a fix for PR23997. The loop vectorizer is not preserving the inbounds property of GEPs that it creates. This is inhibiting some optimizations. This patch preserves the inbounds property in the case where a load/store is being fed by an inbounds GEP. Reviewers: mkuper, javed.absar, hsaito Reviewed By: hsaito Subscribers: dcaballe, hsaito, llvm-commits Differential Revision: https://reviews.llvm.org/D46191 llvm-svn: 331269
* Fix the issue that ComputeValueKnownInPredecessors only handles the case whenWei Mi2018-05-012-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | phi is on lhs of a comparison op. For the following testcase, L1: %t0 = add i32 %m, 7 %t3 = icmp eq i32* %t2, null br i1 %t3, label %L3, label %L2 L2: %t4 = load i32, i32* %t2, align 4 br label %L3 L3: %t5 = phi i32 [ %t0, %L1 ], [ %t4, %L2 ] %t6 = icmp eq i32 %t0, %t5 br i1 %t6, label %L4, label %L5 We know if we go through the path L1 --> L3, %t6 should always be true. However currently, if the rhs of the eq comparison is phi, JumpThreading fails to evaluate %t6 to true. And we know that Instcombine cannot guarantee always canonicalizing phi to the left hand side of the comparison operation according to the operand priority comparison mechanism in instcombine. The patch handles the case when rhs of the comparison op is a phi. Differential Revision: https://reviews.llvm.org/D46275 llvm-svn: 331266
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