[AggressiveInstCombine] add more bitfield test patterns; NFC

Add another baseline for D45986 and a pattern that won't be
matched with that patch.

llvm-svn: 331309

1 files changed, 50 insertions, 4 deletions

diff --git a/llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll b/llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll
index fc3ab6340e1..be59919a800 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/masked-cmp.ll
@@ -3,8 +3,8 @@
 
 ; PR37098 - https://bugs.llvm.org/show_bug.cgi?id=37098
 
-define i32 @two_bit_mask(i32 %x) {
-; CHECK-LABEL: @two_bit_mask(
+define i32 @anyset_two_bit_mask(i32 %x) {
+; CHECK-LABEL: @anyset_two_bit_mask(
 ; CHECK-NEXT:    [[S:%.*]] = lshr i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[O:%.*]] = or i32 [[S]], [[X]]
 ; CHECK-NEXT:    [[R:%.*]] = and i32 [[O]], 1
@@ -16,8 +16,8 @@ define i32 @two_bit_mask(i32 %x) {
   ret i32 %r
 }
 
-define i32 @four_bit_mask(i32 %x) {
-; CHECK-LABEL: @four_bit_mask(
+define i32 @anyset_four_bit_mask(i32 %x) {
+; CHECK-LABEL: @anyset_four_bit_mask(
 ; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[T2:%.*]] = lshr i32 [[X]], 5
 ; CHECK-NEXT:    [[T3:%.*]] = lshr i32 [[X]], 8
@@ -37,3 +37,49 @@ define i32 @four_bit_mask(i32 %x) {
   ret i32 %r
 }
 
+; We're not testing the LSB here, so all of the 'or' operands are shifts.
+
+define i32 @anyset_three_bit_mask_all_shifted_bits(i32 %x) {
+; CHECK-LABEL: @anyset_three_bit_mask_all_shifted_bits(
+; CHECK-NEXT:    [[T1:%.*]] = lshr i32 [[X:%.*]], 3
+; CHECK-NEXT:    [[T2:%.*]] = lshr i32 [[X]], 5
+; CHECK-NEXT:    [[T3:%.*]] = lshr i32 [[X]], 8
+; CHECK-NEXT:    [[O2:%.*]] = or i32 [[T2]], [[T3]]
+; CHECK-NEXT:    [[O3:%.*]] = or i32 [[T1]], [[O2]]
+; CHECK-NEXT:    [[R:%.*]] = and i32 [[O3]], 1
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %t1 = lshr i32 %x, 3
+  %t2 = lshr i32 %x, 5
+  %t3 = lshr i32 %x, 8
+  %o2 = or i32 %t2, %t3
+  %o3 = or i32 %t1, %o2
+  %r = and i32 %o3, 1
+  ret i32 %r
+}
+
+; TODO: Recognize the 'and' sibling pattern. The 'and 1' may not be at the end.
+
+define i64 @allset_four_bit_mask(i64 %x) {
+; CHECK-LABEL: @allset_four_bit_mask(
+; CHECK-NEXT:    [[T1:%.*]] = lshr i64 [[X:%.*]], 1
+; CHECK-NEXT:    [[T2:%.*]] = lshr i64 [[X]], 2
+; CHECK-NEXT:    [[T3:%.*]] = lshr i64 [[X]], 3
+; CHECK-NEXT:    [[T4:%.*]] = lshr i64 [[X]], 4
+; CHECK-NEXT:    [[A1:%.*]] = and i64 [[T4]], 1
+; CHECK-NEXT:    [[A2:%.*]] = and i64 [[T2]], [[A1]]
+; CHECK-NEXT:    [[A3:%.*]] = and i64 [[A2]], [[T1]]
+; CHECK-NEXT:    [[R:%.*]] = and i64 [[A3]], [[T3]]
+; CHECK-NEXT:    ret i64 [[R]]
+;
+  %t1 = lshr i64 %x, 1
+  %t2 = lshr i64 %x, 2
+  %t3 = lshr i64 %x, 3
+  %t4 = lshr i64 %x, 4
+  %a1 = and i64 %t4, 1
+  %a2 = and i64 %t2, %a1
+  %a3 = and i64 %a2, %t1
+  %r = and i64 %a3, %t3
+  ret i64 %r
+}
+