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* [ARM] Dynamic stack alignment for 16-bit ThumbMomchil Velikov2017-10-223-8/+15
| | | | | | | | | | | This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When targeting processors, which support only the 16-bit Thumb instruction set the compiler ignores the alignment attributes of automatic variables and may silently generate incorrect code. Differential revision: https://reviews.llvm.org/D38143 llvm-svn: 316289
* [X86] Add a pass to convert instruction chains between domains.Guy Blank2017-10-228-666/+2513
| | | | | | | | | | | | | | | | | The pass scans the function to find instruction chains that define registers in the same domain (closures). It then calculates the cost of converting the closure to another domain. If found profitable, the instructions are converted to instructions in the other domain and the register classes are changed accordingly. This commit adds the pass infrastructure and a simple conversion from the GPR domain to the Mask domain. Differential Revision: https://reviews.llvm.org/D37251 Change-Id: Ic2cf1d76598110401168326d411128ae2580a604 llvm-svn: 316288
* [mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld.Nitesh Jain2017-10-222-2/+2
| | | | | | | | | | Reviewers: sdardis Subscribers: jaydeep, bhushan, llvm-commits Differential Revision: https://reviews.llvm.org/D38314 llvm-svn: 316287
* [X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper2017-10-221-0/+11
| | | | | | | | corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. llvm-svn: 316285
* [X86] Don't allow gather/scatter to disassembler if memory operand does not ↵Craig Topper2017-10-221-0/+4
| | | | | | | | use a SIB byte. Fixes PR34998. llvm-svn: 316282
* Reverting r316270 due to failing build bots.Aaron Ballman2017-10-211-16/+16
| | | | | | | http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/12899 http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/7951 llvm-svn: 316276
* [X86][SSE] Add extractps/pextrd equivalence to domain tablesSimon Pilgrim2017-10-2113-91/+81
| | | | | | Differential Revision: https://reviews.llvm.org/D39135 llvm-svn: 316274
* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-211-12/+4
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* [PPC CodeGen] Fix the bitreverse.i64 intrinsic.Fangrui Song2017-10-211-16/+16
| | | | | | | | | | Summary: The two 32-bit words were swapped. Subscribers: nemanjai, kbarton Differential Revision: https://reviews.llvm.org/D38705 llvm-svn: 316270
* [X86][SSE] Add missing extractps scheduling testSimon Pilgrim2017-10-211-0/+62
| | | | llvm-svn: 316262
* [LoopInterchange] Fix phi node ordering miscompile.David Green2017-10-211-0/+90
| | | | | | | | | | | The way that splitInnerLoopHeader splits blocks requires that the induction PHI will be the first PHI in the inner loop header. This makes sure that is actually the case when there are both IV and reduction phis. Differential Revision: https://reviews.llvm.org/D38682 llvm-svn: 316261
* [X86] Do not generate __multi3 for mul i128 on X86Craig Topper2017-10-216-4989/+8381
| | | | | | | | | | | | | | | | Summary: __multi3 is not available on x86 (32-bit). Setting lib call name for MULI_128 to nullptr forces DAGTypeLegalizer::ExpandIntRes_MUL to generate instructions for 128-bit multiply instead of a call to an undefined function. This fixes PR20871 though it may be worth looking at why licm and indvars combine to generate 65-bit multiplies in that test. Patch by Riyaz V Puthiyapurayil Reviewers: craig.topper, schweitz Reviewed By: craig.topper, schweitz Subscribers: RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D38668 llvm-svn: 316254
* [Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek2017-10-201-0/+41
| | | | llvm-svn: 316243
* [WebAssembly] MC: Fix crash when -g specified.Sam Clegg2017-10-201-0/+41
| | | | | | | | | At this point we don't output any debug sections or thier relocations. Differential Revision: https://reviews.llvm.org/D39076 llvm-svn: 316240
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-201-1/+1
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* [Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek2017-10-201-0/+16
| | | | llvm-svn: 316236
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-2015-84/+252
| | | | llvm-svn: 316228
* [X86][SSE] Add missing _mm_extract_ps fast-isel testSimon Pilgrim2017-10-201-1/+16
| | | | llvm-svn: 316226
* [x86] avoid FileCheck assert duplication with retl/retq regex; NFCSanjay Patel2017-10-201-118/+58
| | | | | | | | | | | This was suggested in PR35003: https://bugs.llvm.org/show_bug.cgi?id=35003 32-bit checks may be identical to 64-bit (if we avoid those pesky scalar params!). I'll check in the script change shortly assuming this doesn't anger any bots. llvm-svn: 316223
* Make x86 __ehhandler comdat if parent function isDave Lee2017-10-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change comes from using lld for i686-windows-msvc. Before this change, lld emits an error of: error: relocation against symbol in discarded section: .xdata It's possible that this could be addressed in lld, but I think this change is reasonable on its own. At a high level, this is being generated: A (.text comdat) -> B (.text) -> C (.xdata comdat) Where A is a C++ inline function, which references B, an exception handler thunk, which references C, the exception handling info. With this structure, lld will error when applying relocations to B if the C it references has been discarded (some other C has been selected). This change checks if A is comdat, and if so places the exception registration thunk (B) in the comdata group of A (and B). It appears that MSVC makes the __ehhandler function comdat. Is it possible that duplicate thunks are being emitted into the final binary with other linkers, or are they stripping the unused thunks? Reviewers: rnk, majnemer, compnerd, smeenai Reviewed By: rnk, compnerd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38940 llvm-svn: 316219
* [Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek2017-10-201-0/+63
| | | | | | | | | | | Normally, if the registers holding the induction variable's bounds are redefined inside of the loop's body, the loop cannot be converted to a hardware loop. However, if the redefining instruction is actually loading an immediate value into the register, this conversion is both possible and legal (since the immediate itself will be used in the loop setup in the preheader). llvm-svn: 316218
* [X86] Check all CPU target names. Simon Pilgrim2017-10-201-0/+46
| | | | | | We ignore the 32-bit/64-bit triple but I've tried to use i686 triples for CPUs that don't support x86_64 llvm-svn: 316217
* X86 Tests: Add tests for vector permutes with variable indices. NFC.Zvi Rackover2017-10-203-0/+2584
| | | | | | Basic tests which are the equivalent of single-source shufflevector with variable mask. llvm-svn: 316216
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-10-206-11/+10
| | | | | | | This reverts commit r314507, because the original patch is causing test failures. llvm-svn: 316215
* [ARM] Use post-RA MI scheduler when +use-misched is setEugene Leviant2017-10-201-0/+3
| | | | | | Differential revision: https://reviews.llvm.org/D39100 llvm-svn: 316214
* [X86][AVX512] Regenerate regcall tests.Simon Pilgrim2017-10-202-571/+1860
| | | | | | As part of tracking down machine verifier issues (PR27481) llvm-svn: 316213
* [ValueTracking] Enabling ValueTracking patch by default Nikolai Bozhenov2017-10-201-1/+1
| | | | | | | | | | | | | | | | | (recommit #2 after checking for timeout issue). The original patch was an improvement to IR ValueTracking on non-negative integers. It has been checked in to trunk (D18777, r284022). But was disabled by default due to performance regressions. Perf impact has improved. The patch would be enabled by default. Reviewers: reames, hfinkel Differential Revision: https://reviews.llvm.org/D34101 Patch by: Olga Chupina <olga.chupina@intel.com> llvm-svn: 316208
* Add test case for LoopSink passMax Kazantsev2017-10-201-0/+64
| | | | | | | | | | | This test checks that load from constant memory will be sunk regardless of aliasing stores in the loop. Patch by Daniil Suchkov! Differential Revision: https://reviews.llvm.org/D39113 llvm-svn: 316207
* [AVR] Fix the select-mbb-placement-bug.llDylan McKay2017-10-201-3/+3
| | | | llvm-svn: 316205
* [ExecutionEngine] Temporarily remove the ExecutionEngine tls tests.Lang Hames2017-10-202-20/+0
| | | | | | | Will re-enable once I figure out why the necessary runtime functions are missing on some bots. llvm-svn: 316203
* [ExecutionEngine] After a heroic dev-meeting hack session, the JIT supports TLS.Lang Hames2017-10-202-0/+20
| | | | | | Turns on EmulatedTLS support by default in EngineBuilder. ;) llvm-svn: 316200
* Disabling the transformation introduced in r315888Nemanja Ivanovic2017-10-201-1/+1
| | | | | | | The commit at https://reviews.llvm.org/rL315888 is causing some failures with internal testing. Disabling this code until we can resolve the issues. llvm-svn: 316199
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-192-0/+165
| | | | | | | | | | | | | This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
* [X86][AES] Test AES intrinsics on 32/64-bit targets with/without VEX encodingSimon Pilgrim2017-10-191-56/+118
| | | | | | Don't just test on 32-bit llvm-svn: 316176
* The cost of splitting a large vector instruction is not being taken into ↵Graham Yiu2017-10-191-0/+74
| | | | | | | | | | account by the getUserCost function. This was leading to some loops being over unrolled. The cost of a vector instruction is now being multiplied by the cost of the type legalization. This will return a more accurate cost. Committing on behalf on Brad Nemanich (brad.nemanich@ibm.com) Differential Revision: https://reviews.llvm.org/D38961 llvm-svn: 316174
* [Hexagon] Fix store conversion from rr to io in optimize addressing modesKrzysztof Parzyszek2017-10-191-0/+22
| | | | llvm-svn: 316170
* ExecutionEngine: adjust COFF i386 tautological assertsSaleem Abdulrasool2017-10-191-3/+3
| | | | | | | | | Modify static_casts to not be tautological in some COFF i386 relocations. Patch by Alex Langford! llvm-svn: 316169
* [RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expectedAlex Bradbury2017-10-191-0/+3
| | | | | | | This is necessary to avoid an assertion in the included test case and similar assembler inputs. llvm-svn: 316168
* Revert r315992 because of a found miscompilation failureNikolai Bozhenov2017-10-191-10/+10
| | | | llvm-svn: 316164
* [X86] Replace custom scalar integer absolute matching with ISD::ABS lowering.Simon Pilgrim2017-10-191-5/+2
| | | | | | | | | | | | x86 has its own copy of integer absolute pattern matching to combine directly to a SUB+CMOV. This patch removes the x86 combine and adds custom lowering support for ISD::ABS instead, allowing us to use the DAGCombiner version. Additional test cases are already covered by iabs.ll (rL315706 and rL315711). Differential Revision: https://reviews.llvm.org/D38895 llvm-svn: 316162
* [X86] Add scalar (abs (abs x)) -> (abs x) combine test.Simon Pilgrim2017-10-191-0/+19
| | | | | | Before landing D38895 llvm-svn: 316160
* [ARM GlobalISel] Fix liveins in test. NFCDiana Picus2017-10-191-2/+2
| | | | llvm-svn: 316155
* [ARM GlobalISel] Remove redundant testsDiana Picus2017-10-192-548/+0
| | | | | | | These test cases don't really add anything that isn't covered by other tests as well, so we can safely remove them. llvm-svn: 316154
* Fix buffer overflow.Rafael Espindola2017-10-192-0/+3
| | | | | | We were reading past the end of the buffer. llvm-svn: 316143
* GISel: Canonicalize select tests using update_mir_test_checksJustin Bogner2017-10-1843-2349/+2519
| | | | | | | | This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
* AArch64/GISel: Modernize the localizer testJustin Bogner2017-10-181-259/+203
| | | | llvm-svn: 316138
* Canonicalize a large number of mir tests using update_mir_test_checksJustin Bogner2017-10-1852-1494/+1358
| | | | | | | | | | This converts a large and somewhat arbitrary set of tests to use update_mir_test_checks. I ran the script on all of the tests I expect to need to modify for an upcoming mir syntax change and kept the ones that obviously didn't change the tests in ways that might make it harder to understand. llvm-svn: 316137
* Revert "[ScalarEvolution] Handling for ICmp occuring in the evolution chain."Sanjoy Das2017-10-181-19/+0
| | | | | | | This reverts commit r316054. There was some confusion over the review process: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20171016/495884.html llvm-svn: 316129
* Fix lit.site.cfg.py.in after rL316123Sam Clegg2017-10-181-1/+1
| | | | llvm-svn: 316126
* [AVR] Fix the select_mbb_placement_bug.ll testDylan McKay2017-10-181-3/+3
| | | | llvm-svn: 316124
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