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* AMDGPU: Stop reporting an addressing mode for unknown addrspaceMatt Arsenault2016-04-291-4/+20
| | | | | | | | | This was being treated the same as private, which has an immediate offset. For unknown, it probably means it's for a computation not actually being used for accessing memory, so it should not have a nontrivial addressing mode. llvm-svn: 268002
* DivergenceAnalysis: Fix crash with unreachable blocksMatt Arsenault2016-04-291-0/+17
| | | | | | | Unreachable blocks may not be in the dominator tree, so don't crash on them. llvm-svn: 268001
* [ArgumentPromotion] Propagate operand bundles to promoted call sitesDavid Majnemer2016-04-291-0/+31
| | | | | | | | | We neglected to transfer operand bundles when performing argument promotion. This fixes PR27568. llvm-svn: 267986
* [PR25281] Remove AAResultsWrapper from preserved analyses of loop vectorizer.Michael Zolotukhin2016-04-291-0/+59
| | | | | | | We don't preserve AAResults, because, for one, we don't preserve SCEV-AA. That fixes PR25281. llvm-svn: 267980
* RegisterPressure: Fix default lanemask for missing regunit intervalsMatthias Braun2016-04-292-4/+4
| | | | | | | | | | | | | | In case of missing live intervals for a physical registers getLanesWithProperty() would report 0 which was not a safe default in all situations. Add a parameter to pass in a safe default. No testcase because in-tree targets do not skip computing register unit live intervals. Also cleanup the getXXX() functions to not perform the RequireLiveIntervals checks anymore so we do not even need to return safe defaults. llvm-svn: 267977
* [llvm-cov] Don't emit 'nan%' in reportsVedant Kumar2016-04-291-2/+4
| | | | llvm-svn: 267971
* [LoopVectorize] Keep hints from original loop on the vector loopHal Finkel2016-04-291-0/+30
| | | | | | | | | | | | | | | | We need to keep loop hints from the original loop on the new vector loop. Failure to do this meant that, for example: void foo(int *b) { #pragma clang loop unroll(disable) for (int i = 0; i < 16; ++i) b[i] = 1; } this loop would be unrolled. Why? Because we'd vectorize it, thus dropping the hints that unrolling should be disabled, and then we'd unroll it. llvm-svn: 267970
* [llvm-pdbdump] Restore error messages, handle bad block sizesDavid Majnemer2016-04-282-0/+5
| | | | | | | We lost the ability to report errors, bring it back. Also, correctly validate the block size. llvm-svn: 267955
* [llvm-pdbdump] Correctly read data larger than a blockDavid Majnemer2016-04-282-57/+979
| | | | | | | | | A bug was introduced when the code was refactored which resulted in a bad memory access. This fixes PR27565. llvm-svn: 267953
* [LoopDist] Emit optimization remarks (-Rpass*)Adam Nemet2016-04-281-0/+118
| | | | | | | | | | | | | | | | I closely followed the precedents set by the vectorizer: * With -Rpass-missed, the loop is reported with further details pointing to -Rpass--analysis. * -Rpass-analysis reports the details why distribution has failed. * Regardless of -Rpass*, when distribution fails for a loop where distribution was forced with the pragma, a warning is produced according to -Wpass-failed. In this case the analysis info is also printed even without -Rpass-analysis. llvm-svn: 267952
* [Inliner] Preserve llvm.mem.parallel_loop_access metadataHal Finkel2016-04-281-0/+57
| | | | | | | | | | | | | | | | | | | | | | | When inlining a call site with llvm.mem.parallel_loop_access metadata, this metadata needs to be propagated to all cloned memory-accessing instructions. Otherwise, inlining parts of the loop body will invalidate the annotation. With this functionality, we now vectorize the following as expected: void Body(int *res, int *c, int *d, int *p, int i) { res[i] = (p[i] == 0) ? res[i] : res[i] + d[i]; } void Test(int *res, int *c, int *d, int *p, int n) { int i; #pragma clang loop vectorize(assume_safety) for (i = 0; i < 1600; i++) { Body(res, c, d, p, i); } } llvm-svn: 267949
* Read discriminators correctly from object file.Dehao Chen2016-04-282-0/+135
| | | | | | | | | | | | | | | Summary: This is the follow-up patch for http://reviews.llvm.org/D19436 * Update the discriminator reading algorithm to match the assignment algorithm. * Add test to cover the new algorithm. Reviewers: dnovillo, echristo, dblaikie Subscribers: danielcdh, dblaikie, echristo, llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19522 llvm-svn: 267945
* [PowerPC] Fix the EH_SjLj_Setup pseudo.Marcin Koscielnicki2016-04-281-0/+48
| | | | | | | | | | | | | | | | | | | This instruction is just a control flow marker - it should not actually exist in the object file. Unfortunately, nothing catches it before it gets to AsmPrinter. If integrated assembler is used, it's considered to be a normal 4-byte instruction, and emitted as an all-0 word, crashing the program. With external assembler, a comment is emitted. Fixed by setting Size to 0 and handling it in MCCodeEmitter - this means the comment will still be emitted if integrated assembler is not used. This broke an ASan test, which has been disabled for a long time as a result (see the discussion on D19657). We can reenable it once this lands. llvm-svn: 267943
* Fix a bug in llvm-objdump for -private-headers printing the ↵Kevin Enderby2016-04-282-0/+7
| | | | | | | | LC_CODE_SIGNATURE Mach-O load command. rdar://25985653 llvm-svn: 267940
* [RDF] Improve handling of inline-asmKrzysztof Parzyszek2016-04-282-0/+73
| | | | | | | - Keep implicit defs from inline-asm instructions. - Treat register references from inline-asm as fixed. llvm-svn: 267936
* Update llvm-objdump for disassembly of ARM Mach-O files to always include ↵Kevin Enderby2016-04-281-4/+4
| | | | | | | | | | the opcode bytes. As this is the expected behavior of the old darwin otool(1) for ARM Mach-O files. rdar://25896249 llvm-svn: 267929
* Read the rest of the DBI substreams, and parse source info.Zachary Turner2016-04-281-0/+3
| | | | | | | | | | | | | We now read out the rest of the substreams from the DBI streams. One of these substreams, the FileInfo substream, contains information about which source files contribute to each module (aka compiland). This patch additionally parses out the file information from that substream, and dumps it in llvm-pdbdump. Differential Revision: http://reviews.llvm.org/D19634 Reviewed by: ruiu llvm-svn: 267928
* This reverts commit r265505.Kit Barton2016-04-283-111/+0
| | | | | | | Revert "[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance". This patch has caused a functional regression in SPEC2k6 namd, and a performance regression in mesa-pipe. llvm-svn: 267927
* [Hexagon] Add instruction aliases for vector unsigned compare-equalKrzysztof Parzyszek2016-04-281-0/+36
| | | | | | Unsigned compare-equal instructions are mapped to signed compare-equal. llvm-svn: 267925
* AMDGPU: Emit error if too much LDS is usedMatt Arsenault2016-04-282-3/+17
| | | | llvm-svn: 267922
* Reset the TopRPTracker's position in ScheduleDAGMILive::initQueuesKrzysztof Parzyszek2016-04-281-0/+151
| | | | | | | | | | | | | | | | | | | ScheduleDAGMI::initQueues changes the RegionBegin to the first non-debug instruction. Since it does not track register pressure, it does not affect any RP trackers. ScheduleDAGMILive inherits initQueues from ScheduleDAGMI, and it does reset the TopTPTracker in its schedule method. Any derived, target-specific scheduler will need to do it as well, but the TopRPTracker is only exposed as a "const" object to derived classes. Without the ability to modify the tracker directly, this leaves a derived scheduler with a potential of having the TopRPTracker out-of-sync with the CurrentTop. The symptom of the problem: void llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit *, bool): Assertion `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. Differential Revision: http://reviews.llvm.org/D19438 llvm-svn: 267918
* AMDGPU: Fix mishandling array allocations when promoting allocaMatt Arsenault2016-04-283-16/+66
| | | | | | | | The canonical form for allocas is a single allocation of the array type. In case we see a non-canonical array alloca, make sure we aren't replacing this with an array N times smaller. llvm-svn: 267916
* [Hexagon] Define certain aliases for vector instructionsKrzysztof Parzyszek2016-04-281-0/+10
| | | | | | | | | Specifically: Vd = #0 -> Vd = vxor(Vd, Vd) Vdd = #0 -> Vdd.w = vsub(Vdd.w, Vdd.w) Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L) llvm-svn: 267901
* [mips][atomics] Fix partword atomic binary operation implementationSimon Dardis2016-04-281-67/+90
| | | | | | | | | | | | | | | Currently Mips::emitAtomicBinaryPartword() does not properly respect the width of pointers. For MIPS64 this causes the memory address that the ll/sc sequence uses to be truncated. At runtime this causes a segmentation fault. This can be fixed by applying similar changes as r266204, so that a full 64bit pointer is loaded. Reviewers: dsanders Differential Review: http://reviews.llvm.org/D19651 llvm-svn: 267900
* [SLPVectorizer] Extend SLP Vectorizer to deal with aggregates.Arch D. Robison2016-04-281-0/+189
| | | | | | | | The refactoring portion part was done as r267748. http://reviews.llvm.org/D14185 llvm-svn: 267899
* [Hexagon] Handle double-vector registers as new-value producersKrzysztof Parzyszek2016-04-281-0/+12
| | | | | | Patch by Colin LeMahieu. llvm-svn: 267897
* Debug Info: Restore the pre-r240853 behavior for DWARF2 bitfields.Adrian Prantl2016-04-281-1/+1
| | | | | | | | | The DWARF2 specification of DW_AT_bit_offset is ambiguous for little-endian machines, but by restoring to the old behavior we match what debuggers expect and what other popular compilers generate. llvm-svn: 267896
* Debug info: Support DWARF4 bitfields via DW_AT_data_bit_offset.Adrian Prantl2016-04-282-0/+124
| | | | | | | | | | | | | The DWARF2 specification of DW_AT_bit_offset was written from the perspective of a big-endian machine with unclear semantics for other systems. DWARF4 deprecated DW_AT_bit_offset and introduced a new attribute DW_AT_data_bit_offset that simply counts the number of bits from the beginning of the containing entity regardless of endianness. After this patch LLVM emits DW_AT_bit_offset for DWARF 2 or 3 and DW_AT_data_bit_offset when DWARF 4 or later is requested. llvm-svn: 267895
* [RDF] Handle undefined registers in RDF copy propagationKrzysztof Parzyszek2016-04-281-0/+55
| | | | | | | When updating the graph, make sure that new uses without reaching defs are handled correctly. llvm-svn: 267891
* [InstCombine][SSE] Add MOVMSK support to SimplifyDemandedUseBitsSimon Pilgrim2016-04-281-27/+10
| | | | | | | | | | The MOVMSK instructions copies a vector elements' sign bits to the low bits of a scalar register and zeros the high bits. This patch adds MOVMSK support to SimplifyDemandedUseBits so that its aware that the upper bits are known to be zero. It also removes the call to MOVMSK if none of the lower bits are actually required and just returns zero. Differential Revision: http://reviews.llvm.org/D19614 llvm-svn: 267873
* CodeGen: Add DetectDeadLanes pass.Matthias Braun2016-04-281-0/+408
| | | | | | | | | | | | | | | | | | | | The DetectDeadLanes pass performs a dataflow analysis of used/defined subregister lanes across COPY instructions and instructions that will get lowered to copies. It detects dead definitions and uses reading undefined values which are obscured by COPY and subregister usage. These dead definitions cause trouble in the register coalescer which cannot deal with definitions suddenly becoming dead after coalescing COPY instructions. For now the pass only adds dead and undef flags to machine operands. It should be possible to extend it in the future to remove the dead instructions and redo the analysis for the affected virtual registers. Differential Revision: http://reviews.llvm.org/D18427 llvm-svn: 267851
* Update test to use FileCheckSanjay Patel2016-04-281-14/+41
| | | | | | Also, add some metadata to show what that currently looks like. llvm-svn: 267827
* [SystemZ] Support Swift Calling ConventionBryan Chan2016-04-283-0/+627
| | | | | | | | | | | | | | | | Summary: Port rL265480, rL264754, rL265997 and rL266252 to SystemZ, in order to enable the Swift port on the architecture. SwiftSelf and SwiftError are assigned to R10 and R9, respectively, which are normally callee-saved registers. For more information, see: RFC: Implementing the Swift calling convention in LLVM and Clang https://groups.google.com/forum/#!topic/llvm-dev/epDd2w93kZ0 Reviewers: kbarton, manmanren, rjmccall, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19414 llvm-svn: 267823
* LTO: Don't bother trying to mangle unnamed globals, as they can't be ↵Peter Collingbourne2016-04-271-0/+10
| | | | | | | | | | | | | | preserved with MustPreserveSymbols. Summary: Should fix sanitizer-windows bot. Reviewers: joker.eph Subscribers: llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19635 llvm-svn: 267820
* Fix bugs in llvm-objdump printing the last word for -section in non i386 and ↵Kevin Enderby2016-04-272-1/+5
| | | | | | | | | | | x86 files. Two problems, 1) for the last 4 bytes it would print them as separate bytes not a word and 2) it would print the same last byte for those bytes less than a word. rdar://25938224 llvm-svn: 267819
* Parse module information from DBI stream.Zachary Turner2016-04-271-0/+24
| | | | | | | | | | | | This gets more data out of the DBI strema of the PDB. In particular it extracts the metadata for the list of modules (compilands) that this PDB contains info about, and adds support for dumping these fields to llvm-pdbdump. Differential Revision: http://reviews.llvm.org/D19570 Reviewed By: ruiu llvm-svn: 267818
* more buildbot failure fix to r267792Rong Xu2016-04-271-1/+1
| | | | | | __llvm_prf_nm length is embedded in llvm_used. Relax llvm_used check. llvm-svn: 267816
* [PGO] Promote indirect calls to conditional direct calls with value-profileRong Xu2016-04-276-0/+384
| | | | | | | | | | This patch implements the transformation that promotes indirect calls to conditional direct calls when the indirect-call value profile meta-data is available. Differential Revision: http://reviews.llvm.org/D17864 llvm-svn: 267815
* [X86] Enable the post-RA-scheduler for clang's default 32-bit cpu.Mitch Bodart2016-04-271-0/+40
| | | | | | | | | For compilations with no explicit cpu specified, this exhibits nice gains on Silvermont, with neutral performance on big cores. Differential Revision: http://reviews.llvm.org/D19138 llvm-svn: 267809
* Fix a bug in llvm-objdump printing of 32-bit addresses for -section in non ↵Kevin Enderby2016-04-272-0/+4
| | | | | | | | i386 and x86 files. rdar://25896202 llvm-svn: 267807
* [X86][FastISel] Make sure we use the right register class when we select stores.Quentin Colombet2016-04-271-3/+3
| | | | llvm-svn: 267806
* Fix buildbot failure due to r267792Rong Xu2016-04-271-1/+1
| | | | | | Relax the test check as some targets do not have name compression. llvm-svn: 267803
* [Hexagon] Merging nops in to previous packet rather than always creating a ↵Colin LeMahieu2016-04-271-0/+60
| | | | | | new one. llvm-svn: 267798
* [X86] Fix the lowering of TLS calls.Quentin Colombet2016-04-272-4/+9
| | | | | | | | | | | The callseq_end node must be glued with the TLS calls, otherwise, the generic code will miss the uses of the returned value and will mark it dead. Moreover, TLSCall 64-bit pseudo must not set an implicit-use on RDI, the pseudo uses the symbol address at this point not RDI and the lowering will do the right thing. llvm-svn: 267797
* [PGO] Prohibit address recording if the function is both internal and COMDATRong Xu2016-04-271-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D19515 llvm-svn: 267792
* AMDGPU: Account for globals in AMDGPUPromoteAlloca passMatt Arsenault2016-04-271-0/+32
| | | | | | Patch by Bas Nieuwenhuizen llvm-svn: 267791
* Add a test case for the crash fixed with r267037. David Blaikie said it ↵Kevin Enderby2016-04-272-0/+3
| | | | | | | | | would be nice to have! This was crashing llvm-objdump with -macho -objc-meta-data when trying dump a non-existent section. So the test binary is simply created from an empty .s file compiled with: clang -arch armv7 empty.s -c llvm-svn: 267782
* [AArch64] Set correct successors in CMPXCHG pseudo expansion.Ahmed Bougacha2016-04-271-1/+1
| | | | | | | | | | | transferSuccessors() would LoadCmpBB a successor of DoneBB, whereas it should be a successor of the original MBB. Follow-up to r266339. Unfortunately, it's tricky to catch this in the verifier. llvm-svn: 267779
* [ARM] Set correct successors in CMPXCHG pseudo expansion.Ahmed Bougacha2016-04-271-3/+3
| | | | | | | | | | | | | | transferSuccessors() would LoadCmpBB a successor of DoneBB, whereas it should be a successor of the original MBB. The testcase changes are caused by Thumb2SizeReduction, which was previously confused by the broken CFG. Follow-up to r266679. Unfortunately, it's tricky to catch this in the verifier. llvm-svn: 267778
* [InstCombine][AVX2] Add AVX2 per-element vector shift testsSimon Pilgrim2016-04-271-0/+467
| | | | | | At the moment we don't simplify PSRAV/PSRLV/PSLLV intrinsics to generic IR for constant shift amounts, but we could. llvm-svn: 267777
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