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* Fix Windows unwind info for functions in sections other than .textReid Kleckner2014-12-221-2/+72
| | | | | | | | | | | Previously we assumed the section name had the form .text$foo, which is what we used to do for inline functions. If the dollar wasn't present, we'd put unwind data in the .pdata and .xdata sections for the main .text section, which is incorrect. Fixes PR22001. llvm-svn: 224738
* [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.Colin LeMahieu2014-12-222-2/+14
| | | | llvm-svn: 224735
* [Hexagon] Adding classes and load unsigned byte instruction, updating usages.Colin LeMahieu2014-12-221-0/+14
| | | | llvm-svn: 224730
* [x86] Add vector @llvm.ctpop intrinsic custom loweringBruno Cardoso Lopes2014-12-221-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when ctpop is supported for scalar types, the expansion of @llvm.ctpop.vXiY uses vector element extractions, insertions and individual calls to @llvm.ctpop.iY. When not, expansion with bit-math operations is used for the scalar calls. Local haswell measurements show that we can improve vector @llvm.ctpop.vXiY expansion in some cases by using a using a vector parallel bit twiddling approach, based on: v = v - ((v >> 1) & 0x55555555); v = (v & 0x33333333) + ((v >> 2) & 0x33333333); v = ((v + (v >> 4) & 0xF0F0F0F) v = v + (v >> 8) v = v + (v >> 16) v = v & 0x0000003F (from http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel) When scalar ctpop isn't supported, the approach above performs better for v2i64, v4i32, v4i64 and v8i32 (see numbers below). And even when scalar ctpop is supported, this approach performs ~2x better for v8i32. Here, x86_64 implies -march=corei7-avx without ctpop and x86_64h includes ctpop support with -march=core-avx2. == [x86_64h - new] v8i32: 0.661685 v4i32: 0.514678 v4i64: 0.652009 v2i64: 0.324289 == [x86_64h - old] v8i32: 1.29578 v4i32: 0.528807 v4i64: 0.65981 v2i64: 0.330707 == [x86_64 - new] v8i32: 1.003 v4i32: 0.656273 v4i64: 1.11711 v2i64: 0.754064 == [x86_64 - old] v8i32: 2.34886 v4i32: 1.72053 v4i64: 1.41086 v2i64: 1.0244 More work for other vector types will come next. llvm-svn: 224725
* [CodeGenPrepare] Handle properly the promotion of operands when this does notQuentin Colombet2014-12-221-0/+25
| | | | | | | | | generate instructions. Fixes PR21978. Related to <rdar://problem/18310086> llvm-svn: 224717
* AVX-512: Added all forms of BLENDM instructions,Elena Demikhovsky2014-12-223-2/+301
| | | | | | intrinsics, encoding tests for AVX-512F and skx instructions. llvm-svn: 224707
* Lower multiply-negate operation to mneg on AArch64Karthik Bhat2014-12-221-0/+15
| | | | | | | | | | | This patch pattern matches code such as- neg w8, w8 mul w8, w9, w8 to mneg w8, w8, w9 Review: http://reviews.llvm.org/D6754 llvm-svn: 224706
* Convert a few tests to FileCheck. NFC.Rafael Espindola2014-12-224-14/+38
| | | | llvm-svn: 224705
* Enable (sext x) == C --> x == (trunc C) combineMatt Arsenault2014-12-213-7/+542
| | | | | | | | | Extend the existing code which handles this for zext. This makes this more useful for targets with ZeroOrNegativeOne BooleanContent and obsoletes a custom combine SI uses for i1 setcc (sext(i1), 0, setne) since the constant will now be shrunk to i1. llvm-svn: 224691
* ARM: further improve deprecated diagnosis (LDM)Saleem Abdulrasool2014-12-201-5/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM ARM states: LDM/LDMIA/LDMFD: The SP can be in the list. However, ARM deprecates using these instructions with SP in the list. ARM deprecates using these instructions with both the LR and the PC in the list. LDMDA/LDMFA/LDMDB/LDMEA/LDMIB/LDMED: The SP can be in the list. However, instructions that include the SP in the list are deprecated. Instructions that include both the LR and the PC in the list are deprecated. POP: The SP can only be in the list before ARMv7. ARM deprecates any use of ARM instructions that include the SP, and the value of the SP after such an instruction is UNKNOWN. ARM deprecates the use of this instruction with both the LR and the PC in the list. Attempt to diagnose use of deprecated forms of these instructions. This mirrors the previous changes to diagnose use of the deprecated forms of STM in ARM mode. llvm-svn: 224682
* This should have been part of r224676.David Majnemer2014-12-201-2/+2
| | | | llvm-svn: 224677
* InstCombine: Squash an icmp+select into bitwise arithmeticDavid Majnemer2014-12-201-0/+33
| | | | | | | | | (X & INT_MIN) == 0 ? X ^ INT_MIN : X into X | INT_MIN (X & INT_MIN) != 0 ? X ^ INT_MIN : X into X & INT_MAX This fixes PR21993. llvm-svn: 224676
* InstSimplify: Optimize away pointless comparisonsDavid Majnemer2014-12-201-0/+76
| | | | | | | | | (X & INT_MIN) ? X & INT_MAX : X into X & INT_MAX (X & INT_MIN) ? X : X & INT_MAX into X (X & INT_MIN) ? X | INT_MIN : X into X (X & INT_MIN) ? X : X | INT_MIN into X | INT_MIN llvm-svn: 224669
* [x86] Change the test added in r223774 to first check the spelling ofChandler Carruth2014-12-201-26/+33
| | | | | | | | | | | | | | | the error message for a bogus processor, and then look specifically for that error message using FileCheck. I actually tried to write the test this way at first, but drew a blank on how to ensure the error message stayed in sync (oops). Now that I've recalled how to do that, this is clearly better. It also fixes an issue with a malloc implementation that actually prints to stderr in all cases, which was causing problems for some builders it seems. llvm-svn: 224665
* Masked load and store codegen - fixed 128-bit vectorsElena Demikhovsky2014-12-191-8/+78
| | | | | | | The codegen failed on 128-bit types on AVX2. I added patterns and in td files and tests. llvm-svn: 224647
* R600/SI: Only form min/max with 1 use.Matt Arsenault2014-12-193-0/+69
| | | | | | | If the condition is used for something else, this increases the number of instructions. llvm-svn: 224646
* Add printing the LC_ROUTINES load commands with llvm-objdump’s ↵Kevin Enderby2014-12-192-0/+14
| | | | | | -private-headers. llvm-svn: 224627
* Add the ExceptionHandling::MSVC enumerationReid Kleckner2014-12-194-4/+4
| | | | | | | | | | | | | | | It is intended to be used for a family of personality functions that have similar IR preparation requirements. Typically when interoperating with MSVC personality functions, bits of functionality need to be outlined from the main function into helper functions. There is also usually more than one landing pad per invoke, which does not match the LLVM IR landingpad representation. None of this is implemented yet. This change just adds a new enum that is active for *-windows-msvc and delegates to the EH removal preparation pass. No functionality change for other targets. llvm-svn: 224625
* Model sqrtss as a binary operation with one source operand tied to the ↵Sanjay Patel2014-12-191-5/+38
| | | | | | | | | | | destination (PR14221) This is a continuation of r167064 ( http://llvm.org/viewvc/llvm-project?view=revision&revision=167064 ). That patch started to fix PR14221 ( http://llvm.org/bugs/show_bug.cgi?id=14221 ), but it was not completed. Differential Revision: http://reviews.llvm.org/D6330 llvm-svn: 224624
* R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operandTom Stellard2014-12-191-0/+39
| | | | | | | | mubuf instructions now define the soffset field using the SCSrc_32 register class which indicates that only SGPRs and inline constants are allowed. llvm-svn: 224622
* Add printing the LC_SUB_CLIENT load command with llvm-objdump’s ↵Kevin Enderby2014-12-192-0/+7
| | | | | | -private-headers. llvm-svn: 224616
* CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.Peter Collingbourne2014-12-191-0/+19
| | | | llvm-svn: 224615
* [Hexagon] Removing old variants of instructions and updating references.Colin LeMahieu2014-12-191-0/+2
| | | | llvm-svn: 224612
* merge consecutive stores of extracted vector elementsSanjay Patel2014-12-191-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a path to DAGCombiner::MergeConsecutiveStores() to combine multiple scalar stores when the store operands are extracted vector elements. This is a partial fix for PR21711 ( http://llvm.org/bugs/show_bug.cgi?id=21711 ). For the new test case, codegen improves from: vmovss %xmm0, (%rdi) vextractps $1, %xmm0, 4(%rdi) vextractps $2, %xmm0, 8(%rdi) vextractps $3, %xmm0, 12(%rdi) vextractf128 $1, %ymm0, %xmm0 vmovss %xmm0, 16(%rdi) vextractps $1, %xmm0, 20(%rdi) vextractps $2, %xmm0, 24(%rdi) vextractps $3, %xmm0, 28(%rdi) vzeroupper retq To: vmovups %ymm0, (%rdi) vzeroupper retq Patch reviewed by Nadav Rotem. Differential Revision: http://reviews.llvm.org/D6698 llvm-svn: 224611
* [Hexagon] Adding bit extraction and table indexing instructions.Colin LeMahieu2014-12-191-0/+16
| | | | llvm-svn: 224610
* [Hexagon] Adding bit insertion instructions.Colin LeMahieu2014-12-191-0/+8
| | | | llvm-svn: 224609
* [Hexagon] Adding more xtype shift instructions.Colin LeMahieu2014-12-192-0/+22
| | | | llvm-svn: 224608
* Add printing the LC_SUB_LIBRARY load command with llvm-objdump’s ↵Kevin Enderby2014-12-192-0/+7
| | | | | | -private-headers. llvm-svn: 224607
* [Hexagon] Adding xtype shift instructions.Colin LeMahieu2014-12-192-0/+132
| | | | llvm-svn: 224604
* [Hexagon] Adding transfers to and from control registers.Colin LeMahieu2014-12-191-1/+5
| | | | llvm-svn: 224599
* Reapply: [InstCombine] Fix visitSwitchInst to use right operand types for ↵Bruno Cardoso Lopes2014-12-191-0/+30
| | | | | | | | | | | | | | | | | | sub cstexpr The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. Also, fix code to also return the modified switch when only the truncation is performed. This fixes an assertion crash. Differential Revision: http://reviews.llvm.org/D6644 rdar://problem/19191835 llvm-svn: 224588
* use -0.0 when creating an fneg instructionSanjay Patel2014-12-191-1/+1
| | | | | | | | | | | | | | | | | | | Backends recognize (-0.0 - X) as the canonical form for fneg and produce better code. Eg, ppc64 with 0.0: lis r2, ha16(LCPI0_0) lfs f0, lo16(LCPI0_0)(r2) fsubs f1, f0, f1 blr vs. -0.0: fneg f1, f1 blr Differential Revision: http://reviews.llvm.org/D6723 llvm-svn: 224583
* Revert "[InstCombine] Fix visitSwitchInst to use right operand types for sub ↵Bruno Cardoso Lopes2014-12-191-30/+0
| | | | | | | | | | | | | cstexpr" Reverts commit r224574 to appease buildbots: The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. This fixes an assertion crash. llvm-svn: 224576
* [InstCombine] Fix visitSwitchInst to use right operand types for sub cstexprBruno Cardoso Lopes2014-12-191-0/+30
| | | | | | | | | | | | | The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. This fixes an assertion crash. Differential Revision: http://reviews.llvm.org/D6644 rdar://problem/19191835 llvm-svn: 224574
* [Object] Don't crash on empty export lists.Juergen Ributzka2014-12-192-0/+4
| | | | | | | | | | | | Summary: This fixes the exports iterator if the export list is empty. Reviewers: Bigcheese, kledzik Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6732 llvm-svn: 224563
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-191-0/+20
| | | | llvm-svn: 224556
* ConstantFold: Shifting undef by zero results in undefDavid Majnemer2014-12-181-0/+21
| | | | llvm-svn: 224553
* Reverting 224550, was not ready for commit.Colin LeMahieu2014-12-181-20/+0
| | | | llvm-svn: 224552
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-181-0/+20
| | | | llvm-svn: 224550
* Add printing the LC_SUB_UMBRELLA load command with llvm-objdump’s ↵Kevin Enderby2014-12-182-0/+7
| | | | | | -private-headers. llvm-svn: 224548
* Add printing the LC_SUB_FRAMEWORK load command with llvm-objdump’s ↵Kevin Enderby2014-12-182-0/+7
| | | | | | -private-headers. llvm-svn: 224534
* [mips][microMIPS] Fix bugs related to atomic SC/LL instructionsJozef Kolek2014-12-182-20/+62
| | | | | | | | | Fix bugs related to atomic microMIPS SC/LL instructions: While expanding atomic operations the mips32r2 encoding was emitted instead of microMIPS. Differential Revision: http://reviews.llvm.org/D6659 llvm-svn: 224524
* ARM: fix an off-by-one in the register list accessSaleem Abdulrasool2014-12-181-5/+13
| | | | | | | | | Fix an off-by-one access introduced in 224502 for push.w and pop.w with single register operands. Add test cases for both scenarios. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224521
* [mips] Clean up the CodeGen/Mips/inlineasmmemop.ll test. NFC.Toma Tabacu2014-12-181-21/+4
| | | | | | | | | | | | | | | | | | Summary: Improve comments and remove a redundant attribute list. There are no functional changes (to the CHECK's or to the code). Part of these changes were suggested in http://reviews.llvm.org/D6637. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6705 llvm-svn: 224517
* [AVX512] Enable FP arithmetic lowering for AVX512VL subsets.Robert Khasanov2014-12-182-0/+693
| | | | | | | Added RegOp2MemOpTable4 to transform 4th operand from register to memory in merge-masked versions of instructions. Added lowering tests. llvm-svn: 224516
* ARM: improve instruction validation for thumb modeSaleem Abdulrasool2014-12-183-14/+101
| | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
* test: avoid unnecessary temporary filesSaleem Abdulrasool2014-12-181-8/+8
| | | | | | Use pipes and redirect the error output to FileCheck directly. NFC. llvm-svn: 224501
* Add a new string member to the TargetOptions struct for the nameEric Christopher2014-12-185-9/+9
| | | | | | | | | | | | | of the abi we should be using. For targets that don't use the option there's no change, otherwise this allows external users to set the ABI via string and avoid some of the -backend-option pain in clang. Use this option to move the ABI for the ARM port from the Subtarget to the TargetMachine and update the testcases accordingly since it's no longer valid to set via -mattr. llvm-svn: 224492
* Model ARM backend ABI selection after the front end code doing theEric Christopher2014-12-185-7/+8
| | | | | | | | | | | | | | same. This will change the "bare metal" ABI from APCS to AAPCS. The only difference between the front and back end code is that the code for Triple::GNU was added for environment. That will migrate to the front end shortly. Tests updated with the ABI they were originally testing in the case of bare metal (e.g. -mtriple armv7) or with a -gnu for arm-linux triples. llvm-svn: 224489
* Reapply "Linker: Drop superseded subprograms"Duncan P. N. Exon Smith2014-12-182-0/+102
| | | | | | | | | | | | | | | | | | | | This reverts commit r224416, reapplying r224389. The buildbots hadn't recovered after my revert, waiting until David reverted a couple of his commits. It looks like it was just bad timing (where we were both modifying code related to the same assertion). Trying again... Here's the original text: When a function gets replaced by `ModuleLinker`, drop superseded subprograms. This ensures that the "first" subprogram pointing at a function is the same one that `!dbg` references point at. This is a stop-gap fix for PR21910. Notably, this fixes Release+Asserts bootstraps that are currently asserting out in `LexicalScopes::initialize()` due to the explicit instantiations in `lib/IR/Dominators.cpp` eventually getting replaced by -argpromotion. llvm-svn: 224487
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