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* Revert "Revert "[LoopSimplify] Fix updating LCSSA after separating nested ↵Michael Zolotukhin2016-08-071-1/+33
| | | | | | | | | loops."" This reverts commit r277901. Reaaply the commit as it looks like it has nothing to do with the bots failures. llvm-svn: 277946
* [ORC] Re-apply r277896, removing bogus triples and datalayouts that broke testsLang Hames2016-08-062-0/+35
| | | | | | on linux last time. llvm-svn: 277942
* [X86][AVX2] Improve sign/zero extension on AVX2 targetsSimon Pilgrim2016-08-062-24/+10
| | | | | | Split extensions to large vectors into 256-bit chunks - the equivalent of what we do with pre-AVX2 into 128-bit chunks llvm-svn: 277939
* [Coroutines] Passify the build bots. Remove restart-trigger.ll test for nowGor Nishanov2016-08-061-16/+0
| | | | llvm-svn: 277937
* [Coroutines] Part 5: Add CGSCC restart triggerGor Nishanov2016-08-061-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: CoroSplit pass processes the coroutine twice. First, it lets it go through complete IPO optimization pipeline as a single function. It forces restart of the pipeline by inserting an indirect call to an empty function "coro.devirt.trigger" which is devirtualized by CoroElide pass that triggers a restart of the pipeline by CGPassManager. (In later patches, when CoroSplit pass sees the same coroutine the second time, it splits it up, adds coroutine subfunctions to the SCC to be processed by IPO pipeline.) Documentation and overview is here: http://llvm.org/docs/Coroutines.html. Upstreaming sequence (rough plan) 1.Add documentation. (https://reviews.llvm.org/D22603) 2.Add coroutine intrinsics. (https://reviews.llvm.org/D22659) 3.Add empty coroutine passes. (https://reviews.llvm.org/D22847) 4.Add coroutine devirtualization + tests. ab) Lower coro.resume and coro.destroy (https://reviews.llvm.org/D22998) c) Do devirtualization (https://reviews.llvm.org/D23229) 5.Add CGSCC restart trigger + tests. <= we are here 6.Add coroutine heap elision + tests. 7.Add the rest of the logic (split into more patches) Reviewers: mehdi_amini, majnemer Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D23234 llvm-svn: 277936
* [AVX-512] Add AVX-512 scalar CVT instructions to hasUndefRegUpdate.Craig Topper2016-08-062-66/+46
| | | | llvm-svn: 277933
* [AVX-512] Add AVX512 run line to a test and re-generate the checks. Future ↵Craig Topper2016-08-061-265/+835
| | | | | | commits will refine some of the sequences. llvm-svn: 277932
* [X86][SSE] Enable commutation between MOVHLPS and UNPCKHPDSimon Pilgrim2016-08-065-21/+15
| | | | | | | | Assuming SSE2 is available then we can safely commute between these, removing some unnecessary register moves and improving memory folding opportunities. VEX encoded versions don't benefit so I haven't added support to them. llvm-svn: 277930
* [X86][SSE] Regenerate SSE1 shuffle testsSimon Pilgrim2016-08-061-2/+2
| | | | llvm-svn: 277925
* [ValueTracking] Teach computeKnownBits about [su]min/maxDavid Majnemer2016-08-063-7/+19
| | | | | | | Reasoning about a select in terms of a min or max allows us to derive a tigher bound on the result. llvm-svn: 277914
* [InstCombine] Don't coerce non-integral pointers to integersSanjoy Das2016-08-061-0/+28
| | | | | | | | | | Reviewers: majnemer Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D23231 llvm-svn: 277910
* Revert "(refs/bisect/bad) GVN-hoist: enable by default"Matthias Braun2016-08-061-1/+0
| | | | | | | | | | | GVN-Hoist appears to miscompile llvm-testsuite SingleSource/Benchmarks/Misc/fbench.c at the moment. I filed http://llvm.org/PR28880 This reverts commit r277786. llvm-svn: 277909
* Part 4c: Coroutine Devirtualization: Devirtualize coro.resume and coro.destroy.Gor Nishanov2016-08-062-2/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the 4c patch of the coroutine series. CoroElide pass now checks if PostSplit coro.begin is referenced by coro.subfn.addr intrinsics. If so replace coro.subfn.addrs with an appropriate coroutine subfunction associated with that coro.begin. Documentation and overview is here: http://llvm.org/docs/Coroutines.html. Upstreaming sequence (rough plan) 1.Add documentation. (https://reviews.llvm.org/D22603) 2.Add coroutine intrinsics. (https://reviews.llvm.org/D22659) 3.Add empty coroutine passes. (https://reviews.llvm.org/D22847) 4.Add coroutine devirtualization + tests. ab) Lower coro.resume and coro.destroy (https://reviews.llvm.org/D22998) c) Do devirtualization <= we are here 5.Add CGSCC restart trigger + tests. 6.Add coroutine heap elision + tests. 7.Add the rest of the logic (split into more patches) Reviewers: majnemer Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D23229 llvm-svn: 277908
* Revert r277896.Nico Weber2016-08-062-41/+0
| | | | | | | | | | | | | | | | It breaks ExecutionEngine/OrcLazy/weak-function.ll on most bots. Script: -- ... -- Exit Code: 1 Command Output (stderr): -- Could not find main function. llvm-svn: 277907
* CodeGen: If Convert blocks that would form a diamond when tail-merged.Kyle Butt2016-08-061-4/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following function currently relies on tail-merging for if conversion to succeed. The common tail of cond_true and cond_false is extracted, and this then forms a diamond pattern that can be successfully if converted. If this block does not get extracted, either because tail-merging is disabled or the threshold is higher, we should still recognize this pattern and if-convert it. define i32 @t2(i32 %a, i32 %b) nounwind { entry: %tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1] br i1 %tmp1434, label %bb17, label %bb.outer bb.outer: ; preds = %cond_false, %entry %b_addr.021.0.ph = phi i32 [ %b, %entry ], [ %tmp10, %cond_false ] %a_addr.026.0.ph = phi i32 [ %a, %entry ], [ %a_addr.026.0, %cond_false ] br label %bb bb: ; preds = %cond_true, %bb.outer %indvar = phi i32 [ 0, %bb.outer ], [ %indvar.next, %cond_true ] %tmp. = sub i32 0, %b_addr.021.0.ph %tmp.40 = mul i32 %indvar, %tmp. %a_addr.026.0 = add i32 %tmp.40, %a_addr.026.0.ph %tmp3 = icmp sgt i32 %a_addr.026.0, %b_addr.021.0.ph br i1 %tmp3, label %cond_true, label %cond_false cond_true: ; preds = %bb %tmp7 = sub i32 %a_addr.026.0, %b_addr.021.0.ph %tmp1437 = icmp eq i32 %tmp7, %b_addr.021.0.ph %indvar.next = add i32 %indvar, 1 br i1 %tmp1437, label %bb17, label %bb cond_false: ; preds = %bb %tmp10 = sub i32 %b_addr.021.0.ph, %a_addr.026.0 %tmp14 = icmp eq i32 %a_addr.026.0, %tmp10 br i1 %tmp14, label %bb17, label %bb.outer bb17: ; preds = %cond_false, %cond_true, %entry %a_addr.026.1 = phi i32 [ %a, %entry ], [ %tmp7, %cond_true ], [ %a_addr.026.0, %cond_false ] ret i32 %a_addr.026.1 } Without tail-merging or diamond-tail if conversion: LBB1_1: @ %bb @ =>This Inner Loop Header: Depth=1 cmp r0, r1 ble LBB1_3 @ BB#2: @ %cond_true @ in Loop: Header=BB1_1 Depth=1 subs r0, r0, r1 cmp r1, r0 it ne cmpne r0, r1 bgt LBB1_4 LBB1_3: @ %cond_false @ in Loop: Header=BB1_1 Depth=1 subs r1, r1, r0 cmp r1, r0 bne LBB1_1 LBB1_4: @ %bb17 bx lr With diamond-tail if conversion, but without tail-merging: @ BB#0: @ %entry cmp r0, r1 it eq bxeq lr LBB1_1: @ %bb @ =>This Inner Loop Header: Depth=1 cmp r0, r1 ite le suble r1, r1, r0 subgt r0, r0, r1 cmp r1, r0 bne LBB1_1 @ BB#2: @ %bb17 bx lr llvm-svn: 277905
* Revert "[LoopSimplify] Fix updating LCSSA after separating nested loops."Michael Zolotukhin2016-08-061-33/+1
| | | | | | | This reverts commit r277877. Try to appease clang-x64-ninja-win7 buildbot. llvm-svn: 277901
* [ORC] Add (partial) weak symbol support to the CompileOnDemand layer.Lang Hames2016-08-062-0/+41
| | | | | | | | | | | | | | This adds partial support for weak functions to the CompileOnDemandLayer by modifying the addLogicalModule method to check for existing stub definitions before building a new stub for a weak function. This scheme is sufficient to support ODR definitions, but fails for general weak definitions if strong definition is encountered after the first weak definition. (A more extensive refactor will be required to fully support weak symbols). This patch does *not* add weak symbol support to RuntimeDyld: I hope to add that in the near future. llvm-svn: 277896
* [IRCE] Preserve loop-simplify formSanjoy Das2016-08-062-4/+14
| | | | | | | | Fixes PR28764. Right now there is no way to test this, but (as mentioned on the PR) with Michael Zolotukhin's yet to be checked in LoopSimplify verfier, 8 of the llvm-lit tests for IRCE crash. llvm-svn: 277891
* [LoopSimplify] Fix updating LCSSA after separating nested loops.Michael Zolotukhin2016-08-051-1/+33
| | | | | | | | | This fixes PR28825. The problem was that we only checked if a value from a created inner loop is used in the outer loop, and fixed LCSSA for them. But we missed to fixup LCSSA for values used in exits of the outer loop. llvm-svn: 277877
* PowerPC: Add a triple to this testJustin Bogner2016-08-051-1/+1
| | | | | | This is running opt without specifying a triple, which isn't correct. llvm-svn: 277875
* AMDGPU/SI: Increase SGPR limit to 96 on Tonga/IcelandMarek Olsak2016-08-052-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the setting of the Vulkan closed source driver. It decreases the max wave count from 10 to 8. 26010 shaders in 14650 tests Totals: VGPRS: 829593 -> 808440 (-2.55 %) Spilled SGPRs: 81878 -> 42226 (-48.43 %) Spilled VGPRs: 367 -> 358 (-2.45 %) Scratch VGPRs: 1764 -> 1748 (-0.91 %) dwords per thread Code Size: 36677864 -> 35923932 (-2.06 %) bytes There is a massive decrease in SGPR spilling in general and -7.4% spilled VGPRs for DiRT Showdown (= SGPRs spilled to scratch?) Reviewers: arsenm, tstellarAMD, nhaehnle Subscribers: arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D23034 llvm-svn: 277867
* [ARM] Constant Materialize: imms with specific value can be encoded into mov.wWeiming Zhao2016-08-051-3/+57
| | | | | | | | | | | | | | | | | | Summary: Thumb2 supports encoding immediates with specific patterns into mov.w by splatting the low 8 bits into other bytes. I'm resubmitting this patch. The test case in the original commit r277610 does not specify triple, so builds with differnt default triple will have different output. This patch fixed trile as thumb-darwin-apple. Reviewers: john.brawn, jmolloy, bruno Subscribers: jmolloy, aemerson, rengolin, samparker, llvm-commits Differential Revision: https://reviews.llvm.org/D23090 llvm-svn: 277865
* [SCEV] Un-grep'ify tests; NFCSanjoy Das2016-08-052-42/+50
| | | | llvm-svn: 277861
* Replace hot-callsite based heuristic to use its own threshold parameter ↵Dehao Chen2016-08-051-1/+1
| | | | | | | | | | | | | | instead of share inline-hint parameter Summary: Hot callsites should have higher threshold than inline hints. This patch uses separate threshold parameter for hot callsites. Reviewers: davidxl, eraman Subscribers: Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D22368 llvm-svn: 277860
* WholeProgramDevirt: print remarks with devirtualized method names.Ivan Krasin2016-08-052-1/+17
| | | | | | | | | | | | | | | | | | Summary: Chrome on Linux uses WholeProgramDevirt for speed ups, and it's important to detect regressions on both sides: the toolchain, if fewer methods get devirtualized after an update, and Chrome, if an innocently looking change caused many hot methods become virtual again. The need to track devirtualized methods is not Chrome-specific, but it's probably the only user of the pass at this time. Reviewers: kcc Differential Revision: https://reviews.llvm.org/D23219 llvm-svn: 277856
* [ConstantFolding] Don't create illegal (non-integral) inttoptrsSanjoy Das2016-08-051-0/+20
| | | | | | | | | | Reviewers: majnemer, arsenm Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D23182 llvm-svn: 277854
* [SCEV] Don't infinitely recurse on unreachable codeSanjoy Das2016-08-051-0/+28
| | | | llvm-svn: 277848
* Add the first of what will be a long line of additional error checks for ↵Kevin Enderby2016-08-054-2/+11
| | | | | | | | | | | | | invalid Mach-O files. This is where an LC_SEGMENT load command has a fileoff field that extends past the end of the file. Also fix llvm-nm and llvm-size to remove the errorToErrorCode() call so error messages are printed. And needed to update a few test cases now that they do print the error messages just a bit differently. llvm-svn: 277845
* Do not assign new discriminator for all intrinsics.Dehao Chen2016-08-051-0/+6
| | | | | | | | | | | | Summary: We do not care about intrinsic calls when assigning discriminators. Reviewers: davidxl, dnovillo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23212 llvm-svn: 277843
* GlobalISel: clear pending phis after MachineFunction translatedTim Northover2016-08-051-11/+9
| | | | | | | Test is just reordering the existing functions (it would trigger for any function after one with a phi). llvm-svn: 277841
* [X86][SSE] Add initial support for 2 input target shuffle combining.Simon Pilgrim2016-08-052-14/+3
| | | | | | At the moment only the INSERTPS matching can actually use 2 inputs but the plumbing is now in place. llvm-svn: 277839
* GlobalISel: IRTranslate PHI instructionsTim Northover2016-08-051-0/+29
| | | | llvm-svn: 277835
* opt: Adding -O0 to opt toolGor Nishanov2016-08-051-0/+1
| | | | | | | | | | | | | | Summary: Having -O0 in opt allows testing that -O0 optimization pipeline is built correctly. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23208 llvm-svn: 277829
* [PowerPC] Wrong fast-isel codegen for VSX floating-point loadsUlrich Weigand2016-08-051-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were two locations where fast-isel would generate a LFD instruction with a target register class VSFRC instead of F8RC when VSX was enabled. This can ccause invalid registers to be used in certain cases, like: lfd 36, ... instead of using a VSX load instruction. The wrong register number gets silently truncated, causing invalid code to be generated. The first place is PPCFastISel::PPCEmitLoad, which had multiple problems: 1.) The IsVSSRC and IsVSFRC flags are not initialized correctly, since they are computed from resultReg, which is still zero at this point in many cases. Fixed by changing the helper routines to operate on a register class instead of a register and passing in UseRC. 2.) Even with this fixed, Is64VSXLoad is still wrong due to a typo: bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS; bool Is64VSXLoad = IsVSSRC && Opc == PPC::LFD; The second line needs to use isVSFRC (like PPCEmitStore does). 3.) Once both the above are fixed, we're now generating a VSX instruction -- but an incorrect one, since generation of an indexed instruction with null index is wrong. Fixed by copying the code handling the same issue in PPCEmitStore. The second place is PPCFastISel::PPCMaterializeFP, where we would emit an LFD to load a constant from the literal pool, and use the wrong result register class. Fixed by hardcoding a F8RC class even on systems supporting VSX. Fixes: https://llvm.org/bugs/show_bug.cgi?id=28630 Differential Revision: https://reviews.llvm.org/D22632 llvm-svn: 277823
* [SystemZ] Add missing classes and instructionsZhan Jun Liau2016-08-054-0/+360
| | | | | | | | | | | | | | | | Summary: Add instruction formats E, RSI, SSd, SSE, and SSF. Added BRXH, BRXLE, PR, MVCK, STRAG, and ECTG instructions to test out those formats. Reviewers: uweigand Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23179 llvm-svn: 277822
* Actually, r277337 was fine. Just kill the DAGs that made the test allow ↵Benjamin Kramer2016-08-051-20/+20
| | | | | | nondeterminism. llvm-svn: 277821
* [SimplifyCFG] Make range reduction code deterministic.Benjamin Kramer2016-08-051-20/+20
| | | | | | | | | | | This generated IR based on the order of evaluation, which is different between GCC and Clang. With that in mind you get bootstrap miscompares if you compare a Clang built with GCC-built Clang vs. Clang built with Clang-built Clang. Diagnosing that made my head hurt. This also reverts commit r277337, which "fixed" the test case. llvm-svn: 277820
* reduce tests; auto-generate checksSanjay Patel2016-08-051-59/+68
| | | | llvm-svn: 277819
* [PowerPC] fix passing long double arguments to function (soft-float)Strahinja Petrovic2016-08-051-0/+26
| | | | | | | | | | This patch fixes passing long double type arguments to function in soft float mode. If there is less than 4 argument registers free (long double type is mapped in 4 gpr registers in soft float mode) long double type argument must be passed through stack. Differential Revision: https://reviews.llvm.org/D20114. llvm-svn: 277804
* [InstCombine] try to fold (select C, (sext A), B) into logical opsNicolai Haehnle2016-08-052-27/+52
| | | | | | | | | | | | | | | | | | | | | | Summary: Turn (select C, (sext A), B) into (sext (select C, A, B')) when A is i1 and B is a compatible constant, also for zext instead of sext. This will then be further folded into logical operations. The transformation would be valid for non-i1 types as well, but other parts of InstCombine prefer to have sext from non-i1 as an operand of select. Motivated by the shader compiler frontend in Mesa for AMDGPU, which emits i32 for boolean operations. With this change, the boolean logic is fully recovered. Reviewers: majnemer, spatel, tstellarAMD Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22747 llvm-svn: 277801
* [LIT][Darwin] Change %ld64 to be prefixed with DYLD_INSERT_LIBRARIESBruno Cardoso Lopes2016-08-043-5/+8
| | | | | | | | | | | | Followup from r277778, after Mehdi's comments. Expand %ld64 to perform the necessary preload instead, that way new tests do not need to worry about setting up DYLD_INSERT_LIBRARIES themselves. rdar://problem/24300926 llvm-svn: 277788
* GVN-hoist: enable by defaultSebastian Pop2016-08-041-0/+1
| | | | llvm-svn: 277786
* GVN-hoist: fix early exit logicSebastian Pop2016-08-043-2/+30
| | | | | | | | | | The patch splits a complex && if condition into easier to read and understand logic. That wrong early exit condition was letting some instructions with not all operands available pass through when HoistingGeps was true. Differential Revision: https://reviews.llvm.org/D23174 llvm-svn: 277785
* [LV, X86] Be more optimistic about vectorizing shifts.Michael Kuperstein2016-08-042-0/+62
| | | | | | | | | | | | | | | Shifts with a uniform but non-constant count were considered very expensive to vectorize, because the splat of the uniform count and the shift would tend to appear in different blocks. That made the splat invisible to ISel, and we'd scalarize the shift at codegen time. Since r201655, CodeGenPrepare sinks those splats to be next to their use, and we are able to select the appropriate vector shifts. This updates the cost model to to take this into account by making shifts by a uniform cheap again. Differential Revision: https://reviews.llvm.org/D23049 llvm-svn: 277782
* [InstCombine] use m_APInt to allow icmp eq (mul X, C1), C2 folds for splat ↵Sanjay Patel2016-08-041-2/+1
| | | | | | | | | | | | | | | | constant vectors This concludes the splat vector enhancements for foldICmpEqualityWithConstant(). Other commits in this series: https://reviews.llvm.org/rL277762 https://reviews.llvm.org/rL277752 https://reviews.llvm.org/rL277738 https://reviews.llvm.org/rL277731 https://reviews.llvm.org/rL277659 https://reviews.llvm.org/rL277638 https://reviews.llvm.org/rL277629 llvm-svn: 277779
* [LIT][Darwin] Preload libclang_rt.asan_osx_dynamic.dylib when necessaryBruno Cardoso Lopes2016-08-043-3/+30
| | | | | | | | | | | | | | | | | | | | | Green Dragon's darwin stage2 asan bot fails on some checks: http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check test/tools/lto/hide-linkonce-odr.ll test/tools/lto/opt-level.ll ERROR: Interceptors are not working. This may be because AddressSanitizer is loaded too late (e.g. via dlopen) To fix this, %ld64 needs to load 'libclang_rt.asan_osx_dynamic.dylib' before libLTO.dylib, via DYLD_INSERT_LIBRARIES. This won't work by updating config.environment, since some shim binary in the way scrubs the env vars. Instead, provide the path to this lib through %asanrtlib, which can then be used by tests directly with DYLD_INSERT_LIBRARIES. rdar://problem/24300926 llvm-svn: 277778
* GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR.Tim Northover2016-08-045-0/+160
| | | | | | | These are the operations that are trivially identical. Division is omitted for now because you need to use the correct sign/zero extension. llvm-svn: 277775
* GlobalISel: add support for G_MULTim Northover2016-08-041-0/+11
| | | | llvm-svn: 277774
* [CloneFunction] Add a testcase for r277691/r277693David Majnemer2016-08-041-0/+21
| | | | | | | | | PR28848 had a very nice reduction of the underlying cause of the bug. Our ValueMap had, in an entry for an Instruction, a ConstantInt. This is not at all unexpected but should be handled properly. llvm-svn: 277773
* [Mach0YAML] Change n_type from uint8_t to llvm::yaml::Hex8Chris Bieneman2016-08-041-60/+60
| | | | | | Since this field is generally masked, it is way easier to understand it as a Hex value than decimal. llvm-svn: 277770
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