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* test: explicitly use gnu formatSaleem Abdulrasool2016-11-121-2/+2
| | | | | | This should fix the Darwin buildbots. llvm-svn: 286729
* llvm-strings: trivialise logic until we support more optionsSaleem Abdulrasool2016-11-121-0/+13
| | | | | | | | Until we have handling for ignoring unloaded sections, simplify the logic to the point of triviality. This fixes the scanning of archives, particularly when embedded in archives. llvm-svn: 286727
* [AVX-512] Remove the remaining masked shift by immediate or by single value. ↵Craig Topper2016-11-126-382/+381
| | | | | | | | Autoupgrade them to recently introduced unmasked versions and a select. After this I'll add the unmasked intrinsics to InstCombineCalls to finish making our handling of these types of shuffles consistent between AVX-512 and the legacy intrinsics. llvm-svn: 286725
* [OCaml] Clear cross-target test deps when building out-of-treeMichal Gorny2016-11-121-10/+15
| | | | | | | | | | Clear cross-target test dependencies when using LLVM_OCAML_OUT_OF_TREE, in order to make it possible to run check-llvm-bindings-ocaml without rebuilding the whole LLVM. Differential Revision: https://reviews.llvm.org/D26580 llvm-svn: 286720
* [AVX-512] Add unmasked version of shift by immediate and shift by single ↵Craig Topper2016-11-123-0/+866
| | | | | | | | | | | | | | | | | | | element in XMM. Summary: This is the first step towards being able to add the avx512 shift by immediate intrinsics to InstCombineCalls where we aleady support the sse2 and avx2 intrinsics. We need to the unmasked versions so we can avoid having to teach InstCombineCalls that it would need to insert selects sometimes. Instead we'll just add the selects around the new instrinsics in the frontend. This change should also enable the shift by i32 intrinsics to take a non-constant shift value just like the avx2 and sse intrinsics. This will enable us to fix PR30691 once we update clang. Next I'll switch clang to use the new builtins. Then we'll come back to the backend and remove/autoupgrade the old intrinsics. Then I'll work on the same series for variable shifts. Reviewers: RKSimon, zvi, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26333 llvm-svn: 286711
* [AVX-512] Add support for lowering shuffles to VALIGND/VALIGNQCraig Topper2016-11-124-18/+9
| | | | | | | | | | | | Summary: VALIGND and VALIGNQ are similar to PALIGNR but instead of working on a 128-bit lane they work on the entire vector register. This change leverages the shuffle rotate detection code used for PALIGNR to detect these cases. Reviewers: delena, RKSimon Subscribers: Farhana, llvm-commits Differential Revision: https://reviews.llvm.org/D26297 llvm-svn: 286709
* build: add a dependency on llvm-stringsSaleem Abdulrasool2016-11-121-0/+1
| | | | | | Since we now have tests for llvm-strings, add a dependency on the tool. llvm-svn: 286707
* llvm-strings: ensure that the last string is correctly printedSaleem Abdulrasool2016-11-122-0/+4
| | | | | | | We would ignore the last string that appeared if the file ended with a printable character. Ensure that we get the last string. llvm-svn: 286706
* [OCaml] Adapt to the new attribute C API.whitequark2016-11-121-16/+74
| | | | llvm-svn: 286705
* AMDGPU/SI: Promote i16 = fp_[us]int f32 for VITom Stellard2016-11-122-15/+37
| | | | | | | | | | | | Summary: This fixes a regression caused by r286464. Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D26570 llvm-svn: 286687
* AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopiesTom Stellard2016-11-112-0/+64
| | | | | | | | | | | | | | | | | | | | Summary: This pass was assuming that when a PHI instruction defined a register used by another PHI instruction that the defining insstruction would be legalized before the using instruction. This assumption was causing the pass to not legalize some PHI nodes within divergent flow-control. This fixes a bug that was uncovered by r285762. Reviewers: nhaehnle, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D26303 llvm-svn: 286676
* [InstCombine] update test to use FileCheck; NFCSanjay Patel2016-11-111-12/+16
| | | | llvm-svn: 286668
* [tsan][llvm] Implement the function attribute to disable TSan checking at ↵Anna Zaks2016-11-111-0/+35
| | | | | | | | | | | | | | | | | | | | | | | run time This implements a function annotation that disables TSan checking for the function at run time. The benefit over attribute((no_sanitize("thread"))) is that the accesses within the callees will also be suppressed. The motivation for this attribute is a guarantee given by the objective C language that the calls to the reference count decrement and object deallocation will be synchronized. To model this properly, we would need to intercept all ref count decrement calls (which are very common in ObjC due to use of ARC) and also every single message send. Instead, we propose to just ignore all accesses made from within dealloc at run time. The main downside is that this still does not introduce any synchronization, which means we might still report false positives if the code that relies on this synchronization is not executed from within dealloc. However, we have not seen this in practice so far and think these cases will be very rare. Differential Revision: https://reviews.llvm.org/D25858 llvm-svn: 286663
* [LV] Stop saying "use -Rpass-analysis=loop-vectorize"Adam Nemet2016-11-116-11/+11
| | | | | | | | | | | | | | | | | | This is PR28376. Unfortunately given the current structure of optimization diagnostics we lack the capability to tell whether the user has passed -Rpass-analysis=loop-vectorize since this is local to the front-end (BackendConsumer::OptimizationRemarkHandler). So rather than printing this even if the user has already passed -Rpass-analysis, this patch just punts and stops recommending this option. I don't think that getting this right is worth the complexity. Differential Revision: https://reviews.llvm.org/D26563 llvm-svn: 286662
* [PowerPC] Add remaining vector permute builtins in altivec.h - LLVM portionNemanja Ivanovic2016-11-111-0/+70
| | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D26480 Adds all the intrinsics used for various permute builtins that will be added to altivec.h. llvm-svn: 286638
* [cfi] Fix weak functions handling.Evgeniy Stepanov2016-11-111-0/+67
| | | | | | | | | | | | | | | When a function pointer is replaced with a jumptable pointer, special case is needed to preserve the semantics of extern_weak functions. Since a jumptable entry can not be extern_weak, we emulate that behaviour by replacing all references to F (the extern_weak function) with the following expression: F != nullptr ? JumpTablePtr : nullptr. Extra special care is needed for global initializers, since most (or probably all) backends can not lower an initializer that includes this kind of constant expression. Initializers like that are replaced with a global constructor (i.e. a runtime initializer). llvm-svn: 286636
* Fixed the lost FastMathFlags for FCmp operations in SLPVectorizer.Vyacheslav Klochkov2016-11-111-0/+52
| | | | | | | Reviewer: Michael Zolotukhin. Differential Revision: https://reviews.llvm.org/D26543 llvm-svn: 286626
* [InstCombine] add tests to show size-increasing select transformsSanjay Patel2016-11-111-0/+46
| | | | llvm-svn: 286619
* [AArch64] Add test to show narrow zero store merging is disabled with strict ↵Chad Rosier2016-11-111-1/+31
| | | | | | align. NFC. llvm-svn: 286617
* [AArch64] Fix bugs in isel lowering replaceSplatVectorStore.Geoff Berry2016-11-111-0/+45
| | | | | | | | | | | | | | | | | Summary: Fix off-by-one indexing error in loop checking that inserted value was a splat vector. Add code to check that INSERT_VECTOR_ELT nodes constructing the splat vector have the expected constant index values. Reviewers: t.p.northover, jmolloy, mcrosier Subscribers: aemerson, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D26409 llvm-svn: 286616
* [cfi] Implement cfi-icall using inline assembly.Evgeniy Stepanov2016-11-114-24/+93
| | | | | | | | | | | | | | | | | | | | | | | | | The current implementation is emitting a global constant that happens to evaluate to the same bytes + relocation as a jump instruction on X86. This does not work for PIE executables and shared libraries though, because we end up with a wrong relocation type. And it has no chance of working on ARM/AArch64 which use different relocation types for jump instructions (R_ARM_JUMP24) that is never generated for data. This change replaces the constant with module-level inline assembly followed by a hidden declaration of the jump table. Works fine for ARM/AArch64, but has some drawbacks. * Extra symbols are added to the static symbol table, which inflate the size of the unstripped binary a little. Stripped binaries are not affected. This happens because jump table declarations must be external (because their body is in the inline asm). * Original functions that were anonymous are now named <original name>.cfi, and it affects symbolization sometimes. This is necessary because the only user of these functions is the (inline asm) jump table, so they had to be added to @llvm.used, which does not allow unnamed functions. llvm-svn: 286611
* Revert "Use private linkage for MergedGlobals variables" on Darwin.Adrian Prantl2016-11-118-29/+29
| | | | | | | | | | | | | | | | | | | This is a partial revert of r244615 (http://reviews.llvm.org/D11942), which caused a major regression in debug info quality. Turning the artificial __MergedGlobal symbols into private symbols (l__MergedGlobal) means that the linker will not include them in the symbol table of the final executable. Without a symbol table entry dsymutil is not be able to process the debug info for any of the merged globals and thus drops the debug info for all of them. This patch is enabling the old behavior for all MachO targets while leaving all other targets unaffected. rdar://problem/29160481 https://reviews.llvm.org/D26531 llvm-svn: 286607
* [PowerPC] Add vector conversion builtins to altivec.h - LLVM portionNemanja Ivanovic2016-11-111-0/+82
| | | | | | | | | | | This patch corresponds to review: https://reviews.llvm.org/D26307 Adds all the intrinsics used for various conversion builtins that will be added to altivec.h. These are type conversions between various types of vectors. llvm-svn: 286596
* Fix test/tools/gold/X86/thinlto_funcimport.ll on non-X86 hostsJohn Brawn2016-11-111-2/+2
| | | | | | Pass -m elf_x86_64 to gold, as is done in other tests. llvm-svn: 286593
* [AArch64] Enable merging of adjacent zero stores for all subtargets.Chad Rosier2016-11-111-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | This optimization merges adjacent zero stores into a wider store. e.g., strh wzr, [x0] strh wzr, [x0, #2] ; becomes str wzr, [x0] e.g., str wzr, [x0] str wzr, [x0, #4] ; becomes str xzr, [x0] Previously, this was only enabled for Kryo and Cortex-A57. Differential Revision: https://reviews.llvm.org/D26396 llvm-svn: 286592
* [SystemZ] Support CL(G)T instructionsUlrich Weigand2016-11-114-0/+288
| | | | | | | | This adds support for the compare logical and trap (memory) instructions that were added as part of the miscellaneous instruction extensions feature with zEC12. llvm-svn: 286587
* [SystemZ] Support load-and-zero-rightmost-byte facilityUlrich Weigand2016-11-114-0/+458
| | | | | | | | | | This adds support for the LZRF/LZRG/LLZRGF instructions that were added on z13, and uses them for code generation were appropriate. SystemZDAGToDAGISel::tryRISBGZero is updated again to prefer LLZRGF over RISBG where both would be possible. llvm-svn: 286586
* [SystemZ] Use LLGT(R) instructionsUlrich Weigand2016-11-114-0/+210
| | | | | | | | | | | | | This adds support for the 31-to-64-bit zero extension instructions LLGT and LLGTR and uses them for code generation where appropriate. Since this operation can also be performed via RISBG, we have to update SystemZDAGToDAGISel::tryRISBGZero so that we prefer LLGT over RISBG in case both are possible. The patch includes some simplification to the tryRISBGZero code; this is not intended to cause any (further) functional change in codegen. llvm-svn: 286585
* [SelectionDAG] Add support for vector demandedelts in BSWAP opcodesSimon Pilgrim2016-11-111-6/+2
| | | | llvm-svn: 286582
* [X86] Add knownbits vector BSWAP testSimon Pilgrim2016-11-111-0/+22
| | | | | | In preparation for demandedelts support llvm-svn: 286579
* [SelectionDAG] Add support for vector demandedelts in UREM/SREM opcodesSimon Pilgrim2016-11-111-70/+4
| | | | llvm-svn: 286578
* [X86] Add knownbits vector UREM/SREM testsSimon Pilgrim2016-11-111-0/+116
| | | | | | In preparation for demandedelts support llvm-svn: 286577
* [SelectionDAG] Add support for vector demandedelts in UDIV opcodesSimon Pilgrim2016-11-111-50/+2
| | | | llvm-svn: 286576
* [X86] Add knownbits vector UDIV testSimon Pilgrim2016-11-111-0/+64
| | | | | | In preparation for demandedelts support llvm-svn: 286575
* [ARM] Add plumbing for GlobalISelDiana Picus2016-11-112-0/+11
| | | | | | Add GlobalISel skeleton, up to the point where we can select a ret void. llvm-svn: 286573
* ScheduleDAGInstrs: Add condjump deps to addSchedBarrierDeps()Matthias Braun2016-11-1112-27/+41
| | | | | | | | | | | | | | | addSchedBarrierDeps() is supposed to add use operands to the ExitSU node. The current implementation adds uses for calls/barrier instruction and the MBB live-outs in all other cases. The use operands of conditional jump instructions were missed. Also added code to macrofusion to set the latencies between nodes to zero to avoid problems with the fusing nodes lingering around in the pending list now. Differential Revision: https://reviews.llvm.org/D25140 llvm-svn: 286544
* Revert "[AMDGPU] Allow hoisting of comparisons out of a loop and eliminate ↵Stanislav Mekhanoshin2016-11-112-49/+3
| | | | | | | | condition copies" This reverts commit r286171, it breaks piglit test fs-discard-exit-2 llvm-svn: 286530
* ScheduleDAGInstrs: Ignore dependencies of constant physregsMatthias Braun2016-11-103-3/+32
| | | | | | | | | There is no need to track dependencies for constant physregs, as they don't change their value no matter in what order you read/write to them. Differential Revision: https://reviews.llvm.org/D26221 llvm-svn: 286526
* [SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodesSimon Pilgrim2016-11-101-22/+4
| | | | llvm-svn: 286516
* [LSR] Tweak loop-strength-reduce-crash test. Test-only change.Justin Lebar2016-11-101-3/+4
| | | | | | Run opt instead of llc, and update the comment. llvm-svn: 286515
* IR: Introduce inrange attribute on getelementptr indices.Peter Collingbourne2016-11-103-0/+56
| | | | | | | | | | | | | | | | | If the inrange keyword is present before any index, loading from or storing to any pointer derived from the getelementptr has undefined behavior if the load or store would access memory outside of the bounds of the element selected by the index marked as inrange. This can be used, e.g. for alias analysis or to split globals at element boundaries where beneficial. As previously proposed on llvm-dev: http://lists.llvm.org/pipermail/llvm-dev/2016-July/102472.html Differential Revision: https://reviews.llvm.org/D22793 llvm-svn: 286514
* [X86] Updated knownbits vector ADD/SUB testSimon Pilgrim2016-11-101-17/+37
| | | | | | In preparation for demandedelts support llvm-svn: 286513
* [X86] Add knownbits vector ADD testSimon Pilgrim2016-11-101-0/+17
| | | | llvm-svn: 286511
* [SelectionDAG] Add support for splatted vectors in SUB opcodeSimon Pilgrim2016-11-101-8/+2
| | | | llvm-svn: 286509
* [X86] Add knownbits vector SUB testSimon Pilgrim2016-11-101-0/+23
| | | | llvm-svn: 286508
* RegisterCoalescer: Ignore interferences for constant physregsMatthias Braun2016-11-102-2/+32
| | | | | | | | | | | When copying to/from a constant register interferences can be ignored. Also update the documentation for isConstantPhysReg() to make it more obvious that this transformation is valid. Differential Revision: https://reviews.llvm.org/D26106 llvm-svn: 286503
* AMDGPU: Emit runtime metadata as a note element in .note sectionYaxun Liu2016-11-104-72/+24
| | | | | | | | | | | | Currently runtime metadata is emitted as an ELF section with name .AMDGPU.runtime_metadata. However there is a standard way to convey vendor specific information about how to run an ELF binary, which is called vendor-specific note element (http://www.netbsd.org/docs/kernel/elf-notes.html). This patch lets AMDGPU backend emits runtime metadata as a note element in .note section. Differential Revision: https://reviews.llvm.org/D25781 llvm-svn: 286502
* [OptDiag] Remove non-printable chars from function nameAdam Nemet2016-11-101-1/+1
| | | | | | | The r283656 did this in the remark arguments. We also need to do this in the main function attribute as that is written to YAML as well. llvm-svn: 286482
* [SelectionDAG] Add support for vector demandedelts in TRUNCATE opcodesSimon Pilgrim2016-11-101-12/+2
| | | | llvm-svn: 286481
* [X86] Add knownbits vector TRUNC testSimon Pilgrim2016-11-101-0/+27
| | | | | | In preparation for demandedelts support llvm-svn: 286477
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