[SystemZ] Use LLGT(R) instructions

This adds support for the 31-to-64-bit zero extension instructions
LLGT and LLGTR and uses them for code generation where appropriate.

Since this operation can also be performed via RISBG, we have to
update SystemZDAGToDAGISel::tryRISBGZero so that we prefer LLGT
over RISBG in case both are possible.  The patch includes some
simplification to the tryRISBGZero code; this is not intended
to cause any (further) functional change in codegen.

llvm-svn: 286585

4 files changed, 210 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/SystemZ/int-conv-12.ll b/llvm/test/CodeGen/SystemZ/int-conv-12.ll
new file mode 100644
index 00000000000..bedd295782e
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/int-conv-12.ll
@@ -0,0 +1,133 @@
+; Test 31-to-64 bit zero extensions.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test register extension, starting with an i64.
+define i64 @f1(i64 %a) {
+; CHECK-LABEL: f1:
+; CHECK: llgtr %r2, %r2
+; CHECK: br %r14
+  %ext = and i64 %a, 2147483647
+  ret i64 %ext
+}
+
+; Test register extension, starting with an i32.
+define i64 @f2(i32 %a) {
+; CHECK-LABEL: f2:
+; CHECK: llgtr %r2, %r2
+; CHECK: br %r14
+  %and = and i32 %a, 2147483647
+  %ext = zext i32 %and to i64
+  ret i64 %ext
+}
+
+; ... and the other way around.
+define i64 @f3(i32 %a) {
+; CHECK-LABEL: f3:
+; CHECK: llgtr %r2, %r2
+; CHECK: br %r14
+  %ext = zext i32 %a to i64
+  %and = and i64 %ext, 2147483647
+  ret i64 %and
+}
+
+; Check LLGT with no displacement.
+define i64 @f4(i32 *%src) {
+; CHECK-LABEL: f4:
+; CHECK: llgt %r2, 0(%r2)
+; CHECK: br %r14
+  %word = load i32, i32 *%src
+  %ext = zext i32 %word to i64
+  %and = and i64 %ext, 2147483647
+  ret i64 %and
+}
+
+; ... and the other way around.
+define i64 @f5(i32 *%src) {
+; CHECK-LABEL: f5:
+; CHECK: llgt %r2, 0(%r2)
+; CHECK: br %r14
+  %word = load i32, i32 *%src
+  %and = and i32 %word, 2147483647
+  %ext = zext i32 %and to i64
+  ret i64 %ext
+}
+
+; Check the high end of the LLGT range.
+define i64 @f6(i32 *%src) {
+; CHECK-LABEL: f6:
+; CHECK: llgt %r2, 524284(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%src, i64 131071
+  %word = load i32 , i32 *%ptr
+  %ext = zext i32 %word to i64
+  %and = and i64 %ext, 2147483647
+  ret i64 %and
+}
+
+; Check the next word up, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define i64 @f7(i32 *%src) {
+; CHECK-LABEL: f7:
+; CHECK: agfi %r2, 524288
+; CHECK: llgt %r2, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%src, i64 131072
+  %word = load i32 , i32 *%ptr
+  %ext = zext i32 %word to i64
+  %and = and i64 %ext, 2147483647
+  ret i64 %and
+}
+
+; Check the high end of the negative LLGT range.
+define i64 @f8(i32 *%src) {
+; CHECK-LABEL: f8:
+; CHECK: llgt %r2, -4(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%src, i64 -1
+  %word = load i32 , i32 *%ptr
+  %ext = zext i32 %word to i64
+  %and = and i64 %ext, 2147483647
+  ret i64 %and
+}
+
+; Check the low end of the LLGT range.
+define i64 @f9(i32 *%src) {
+; CHECK-LABEL: f9:
+; CHECK: llgt %r2, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%src, i64 -131072
+  %word = load i32 , i32 *%ptr
+  %ext = zext i32 %word to i64
+  %and = and i64 %ext, 2147483647
+  ret i64 %and
+}
+
+; Check the next word down, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define i64 @f10(i32 *%src) {
+; CHECK-LABEL: f10:
+; CHECK: agfi %r2, -524292
+; CHECK: llgt %r2, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32, i32 *%src, i64 -131073
+  %word = load i32 , i32 *%ptr
+  %ext = zext i32 %word to i64
+  %and = and i64 %ext, 2147483647
+  ret i64 %and
+}
+
+; Check that LLGT allows an index.
+define i64 @f11(i64 %src, i64 %index) {
+; CHECK-LABEL: f11:
+; CHECK: llgt %r2, 524287(%r3,%r2)
+; CHECK: br %r14
+  %add1 = add i64 %src, %index
+  %add2 = add i64 %add1, 524287
+  %ptr = inttoptr i64 %add2 to i32 *
+  %word = load i32 , i32 *%ptr
+  %ext = zext i32 %word to i64
+  %and = and i64 %ext, 2147483647
+  ret i64 %and
+}
+
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index cb163271b6c..26eb4564d3f 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -5356,6 +5356,45 @@
 # CHECK: llgf %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x16
 
+# CHECK: llgtr %r0, %r15
+0xb9 0x17 0x00 0x0f
+
+# CHECK: llgtr %r7, %r8
+0xb9 0x17 0x00 0x78
+
+# CHECK: llgtr %r15, %r0
+0xb9 0x17 0x00 0xf0
+
+# CHECK: llgt %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x17
+
+# CHECK: llgt %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x17
+
+# CHECK: llgt %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x17
+
+# CHECK: llgt %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x17
+
+# CHECK: llgt %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x17
+
+# CHECK: llgt %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x17
+
+# CHECK: llgt %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x17
+
+# CHECK: llgt %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x17
+
+# CHECK: llgt %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x17
+
+# CHECK: llgt %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0x17
+
 # CHECK: llghr %r0, %r15
 0xb9 0x85 0x00 0x0f
 
diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s
index 49b4a0b8233..5a2e63a5e85 100644
--- a/llvm/test/MC/SystemZ/insn-bad.s
+++ b/llvm/test/MC/SystemZ/insn-bad.s
@@ -2081,6 +2081,14 @@
 	llgc	%r0, 524288
 
 #CHECK: error: invalid operand
+#CHECK: llgt	%r0, -524289
+#CHECK: error: invalid operand
+#CHECK: llgt	%r0, 524288
+
+	llgt	%r0, -524289
+	llgt	%r0, 524288
+
+#CHECK: error: invalid operand
 #CHECK: llgf	%r0, -524289
 #CHECK: error: invalid operand
 #CHECK: llgf	%r0, 524288
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 854cf1e0250..39274b44bec 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -6741,6 +6741,36 @@
 	llgcr	%r7, %r8
 	llgcr	%r15, %r0
 
+#CHECK: llgt	%r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x17]
+#CHECK: llgt	%r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x17]
+#CHECK: llgt	%r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x17]
+#CHECK: llgt	%r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x17]
+#CHECK: llgt	%r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x17]
+#CHECK: llgt	%r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x17]
+#CHECK: llgt	%r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x17]
+#CHECK: llgt	%r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x17]
+#CHECK: llgt	%r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x17]
+#CHECK: llgt	%r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x17]
+
+	llgt	%r0, -524288
+	llgt	%r0, -1
+	llgt	%r0, 0
+	llgt	%r0, 1
+	llgt	%r0, 524287
+	llgt	%r0, 0(%r1)
+	llgt	%r0, 0(%r15)
+	llgt	%r0, 524287(%r1,%r15)
+	llgt	%r0, 524287(%r15,%r1)
+	llgt	%r15, 0
+
+#CHECK: llgtr	%r0, %r15               # encoding: [0xb9,0x17,0x00,0x0f]
+#CHECK: llgtr	%r7, %r8                # encoding: [0xb9,0x17,0x00,0x78]
+#CHECK: llgtr	%r15, %r0               # encoding: [0xb9,0x17,0x00,0xf0]
+
+	llgtr	%r0, %r15
+	llgtr	%r7, %r8
+	llgtr	%r15, %r0
+
 #CHECK: llgf	%r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x16]
 #CHECK: llgf	%r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x16]
 #CHECK: llgf	%r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x16]