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* Make DW_AT_[MIPS_]linkage_name optional, and off by default for SCE.Paul Robinson2015-08-1114-24/+95
| | | | | | | | | | | | | | Mangled "linkage" names can be huge, and if the debugger (or other tools) have no use for them, the size savings can be very impressive (on the order of 40%). Add one test for controlling behavior, and modify a number of tests to either stop using linkage names, or make llc emit them (so these tests will still run when the default triple is for PS4). Differential Revision: http://reviews.llvm.org/D11374 llvm-svn: 244678
* Fix PR24354.Sanjoy Das2015-08-111-0/+33
| | | | | | | | | | `InstCombiner::OptimizeOverflowCheck` was asserting an invariant (operands to binary operations are ordered by decreasing complexity) that wasn't really an invariant. Fix this by instead having `InstCombiner::OptimizeOverflowCheck` establish the invariant if it does not hold. llvm-svn: 244676
* WebAssembly: implement comparison.JF Bastien2015-08-114-0/+312
| | | | | | | | | | | | Some of the FP comparisons (ueq, one, ult, ule, ugt, uge) are currently broken, I'll fix them in a follow-up. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11924 llvm-svn: 244665
* [x86] enable machine combiner reassociations for 128-bit vector ↵Sanjay Patel2015-08-112-2/+46
| | | | | | single/double multiplies llvm-svn: 244657
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-111-0/+15
| | | | | | Also, add a test for optsize because this was not part of any existing regression test. llvm-svn: 244651
* SelectionDAG: Prefer to combine multiplication with less uses for fmaJingyue Wu2015-08-111-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For example: s6 = s0*s5; s2 = s6*s6 + s6; ... s4 = s6*s3; We notice that it is possible for s2 is folded to fma (s0, s5, fmul (s6 s6)). This only happens when Aggressive is true, otherwise hasOneUse() check already prevents from folding the multiplication with more uses. Test Plan: test/CodeGen/NVPTX/fma-assoc.ll Patch by Xuetian Weng Reviewers: hfinkel, apazos, jingyue, ohsallen, arsenm Subscribers: arsenm, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D11855 llvm-svn: 244649
* [LowerSwitch] Fix a bug when LowerSwitch deletes the default blockChen Li2015-08-111-0/+27
| | | | | | | | | | | | Summary: LowerSwitch crashed with the attached test case after deleting the default block. This happened because the current implementation of deleting dead blocks is wrong. After the default block being deleted, it contains no instruction or terminator, and it should no be traversed anymore. However, since the iterator is advanced before processSwitchInst() function is executed, the block advanced to could be deleted inside processSwitchInst(). The deleted block would then be visited next and crash dyn_cast<SwitchInst>(Cur->getTerminator()) because Cur->getTerminator() returns a nullptr. This patch fixes this problem by recording dead default blocks into a list, and delete them after all processSwitchInst() has been done. It still possible to visit dead default blocks and waste time process them. But it is a compile time issue, and I plan to have another patch to add support to skip dead blocks. Reviewers: kariddi, resistor, hans, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11852 llvm-svn: 244642
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-111-13/+4
| | | | llvm-svn: 244631
* add missing tests for powi expansion with size optimizationsSanjay Patel2015-08-111-0/+27
| | | | | | The minsize test will be fixed in the next commit. llvm-svn: 244630
* fixed to use FileCheckSanjay Patel2015-08-111-5/+15
| | | | llvm-svn: 244627
* fixed to test attribute, rather than CPUSanjay Patel2015-08-111-1/+1
| | | | llvm-svn: 244625
* fix typos; NFCSanjay Patel2015-08-111-1/+1
| | | | llvm-svn: 244619
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-111-7/+32
| | | | llvm-svn: 244617
* [GlobalMerge] Use private linkage for MergedGlobals variablesJohn Brawn2015-08-1110-66/+57
| | | | | | | | | | | | | | | Other objects can never reference the MergedGlobals symbol so external linkage is never needed. Using private instead of internal linkage means the object is more similar to what it looks like when global merging is not enabled, with the only difference being that the merged variables are addressed indirectly relative to the start of the section they are in. Also add aliases for merged variables with internal linkage, as this also makes the object be more like what it is when they are not merged. Differential Revision: http://reviews.llvm.org/D11942 llvm-svn: 244615
* Fix InstCombine test: invalid CHECK line slipped in r231270Mehdi Amini2015-08-111-1/+2
| | | | | | | | | | | | | | I incorrectly wrote CHECK-NEXT with followin with ':', the check was ignored by FileCheck. The non-inbound GEP is folded here because the DataLayout is no longer optional, the fold was originally guarded with a comment that said: We need TD information to know the pointer size unless this is inbounds. Now we always have "TD information" and perform the fold. Thanks Jonathan Roelofs for noticing. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 244613
* remove unnecessary settings/attributes from test caseSanjay Patel2015-08-111-6/+6
| | | | llvm-svn: 244612
* delete FIXME comment; it's fixedSanjay Patel2015-08-111-2/+0
| | | | llvm-svn: 244605
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-111-4/+5
| | | | llvm-svn: 244604
* add missing test for machine combiner when optimizing for sizeSanjay Patel2015-08-111-0/+30
| | | | | | The minsize test will be fixed in the next commit. llvm-svn: 244603
* [X86] Allow merging of immediates within a basic block for code size savingsMichael Kuperstein2015-08-112-85/+82
| | | | | | | | | | | First step in preventing immediates that occur more than once within a single basic block from being pulled into their users, in order to prevent unnecessary large instruction encoding .Currently enabled only when optimizing for size. Patch by: zia.ansari@intel.com Differential Revision: http://reviews.llvm.org/D11363 llvm-svn: 244601
* [AArch64] Match fminnum/fmaxnum for vector fminnm/fmaxnm instead of an ↵James Molloy2015-08-112-11/+20
| | | | | | | | | | | intrinsic. Lower Intrinsic::aarch64_neon_fmin/fmax to fminnum/fmannum and match that instead. Minimal functional change: - Extra tests added because coverage of scalar fminnm/fmaxnm instructions was nonexistant. - f16 test updated because now we actually generate scalar fminnm/fmaxnm we no longer need to bail out to a libcall! llvm-svn: 244595
* [X86] Add SAL mnemonics for Intel syntaxMarina Yatsina2015-08-111-0/+3
| | | | | | | | SAL and SHL instructions perform the same operation Differential Revision: http://reviews.llvm.org/D11882 llvm-svn: 244588
* [X86] Fix REPE, REPZ, REPNZ for intel syntaxMarina Yatsina2015-08-111-0/+13
| | | | | | | | | REPE, REPZ, REPNZ, REPNE should have mnemonics for Intel syntax as well. Currently using these instructions causes compilation errors for Intel syntax. Differential Revision: http://reviews.llvm.org/D11794 llvm-svn: 244584
* [X86] Fix imul alias for intel syntaxMarina Yatsina2015-08-111-0/+7
| | | | | | | | | The "imul reg, imm" alias is not defined for intel syntax. In intel syntax there is no w/l/q suffix for the imul instruction. Differential Revision: http://reviews.llvm.org/D11887 llvm-svn: 244582
* Add support for floating-point minnum and maxnumJames Molloy2015-08-111-0/+156
| | | | | | | | | | | | | | | | | The select pattern recognition in ValueTracking (as used by InstCombine and SelectionDAGBuilder) only knew about integer patterns. This teaches it about minimum and maximum operations. matchSelectPattern() has been extended to return a struct containing the existing Flavor and a new enum defining the pattern's behavior when given one NaN operand. C minnum() is defined to return the non-NaN operand in this case, but the idiomatic C "a < b ? a : b" would return the NaN operand. ARM and AArch64 at least have different instructions for these different cases. llvm-svn: 244580
* [mips] Remap move as or.Vasileios Kalintiris2015-08-1139-43/+97
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
* [X86] When optimizing for minsize, use POP for small post-call stack clean-upMichael Kuperstein2015-08-112-2/+63
| | | | | | | | | | | | | | | | When optimizing for size, replace "addl $4, %esp" and "addl $8, %esp" following a call by one or two pops, respectively. We don't try to do it in general, but only when the stack adjustment immediately follows a call - which is the most common case. That allows taking a short-cut when trying to find a free register to pop into, instead of a full-blown liveness check. If the adjustment immediately follows a call, then every register the call clobbers but doesn't define should be dead at that point, and can be used. Differential Revision: http://reviews.llvm.org/D11749 llvm-svn: 244578
* Allow PeepholeOptimizer to fold a few more casesMichael Kuperstein2015-08-112-13/+10
| | | | | | | | | | The condition for clearing the folding candidate list was clamped together with the "uninteresting instruction" condition. This is too conservative, e.g. we don't need to clear the list when encountering an IMPLICIT_DEF. Differential Revision: http://reviews.llvm.org/D11591 llvm-svn: 244577
* [GMR] Be a bit smarter about which globals don't alias when doing recursive ↵Michael Kuperstein2015-08-111-4/+7
| | | | | | | | | | lookups Should hopefully fix the remainder of PR24288. Differential Revision: http://reviews.llvm.org/D11900 llvm-svn: 244575
* [RuntimeDyld][AArch64] Add explicit addends before calling relocationValueRef.Lang Hames2015-08-111-0/+12
| | | | | | relocationValueRef uses the addend, so it has to be set before the call. llvm-svn: 244574
* Enable five passing dsymutil tests on Windows. Yaron Keren2015-08-115-5/+0
| | | | | | | These tests pass with Windows 7 x64 + MSYS2. I'll see if the bots like them as well and disable the failing ones. llvm-svn: 244572
* [IR] Verify EH pad predecessorsDavid Majnemer2015-08-111-6/+44
| | | | | | | Make sure that an EH pad's predecessors are using their unwind edge to transfer control to the EH pad. llvm-svn: 244563
* WebAssembly: add basic floating-point testsJF Bastien2015-08-112-0/+138
| | | | | | | | | | Summary: I somehow forgot to add these when I added the basic floating-point opcodes. Also remove ceil/floor/trunc/nearestint for now, and add them only when properly tested. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11927 llvm-svn: 244562
* Print vectorization analysis when loop hint is specified.Tyler Nowicki2015-08-113-3/+3
| | | | | | This patch and a relatec clang patch solve the problem of having to explicitly enable analysis when specifying a loop hint pragma to get the diagnostics. Passing AlwasyPrint as the pass name (see below) causes the front-end to print the diagnostic if the user has specified '-Rpass-analysis' without an '=<target-pass>’. Users of loop hints can pass that compiler option without having to specify the pass and they will get diagnostics for only those loops with loop hints. llvm-svn: 244555
* WebAssembly: simply assert on SNaN and NaNs with payloadsJF Bastien2015-08-111-2/+2
| | | | | | | | | | Summary: convertToHexString doesn't represent them correctly at this point in time. This is a follow-up to sunfish's suggestion in D11914. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11925 llvm-svn: 244551
* MIR Serialization: Serialize UsedPhysRegMask from the machine register info.Alex Lorenz2015-08-111-0/+113
| | | | | | | | | | | | This commit serializes the UsedPhysRegMask register mask from the machine register information class. The mask is serialized as an inverted 'calleeSavedRegisters' mask to keep the output minimal. This commit also allows the MIR parser to infer this mask from the register mask operands if the machine function doesn't specify it. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244548
* [libFuzzer] don't crash if the condition in a switch has unusual type (e.g. i72)Kostya Serebryany2015-08-111-0/+24
| | | | llvm-svn: 244544
* Address post-commit review from r243378.Sanjoy Das2015-08-111-0/+1
| | | | | | This checks that bork_directive occurs exactly twice in the test output. llvm-svn: 244543
* MIR Parser: Report an error when a stack object is redefined.Alex Lorenz2015-08-101-0/+38
| | | | llvm-svn: 244536
* Add lduw and lwua aliases for SPARCv9.Joerg Sonnenberger2015-08-101-0/+17
| | | | llvm-svn: 244535
* MIR Parser: Report an error when a fixed stack object is redefined.Alex Lorenz2015-08-101-0/+30
| | | | llvm-svn: 244534
* Load/store for float registers from/to alternate space.Joerg Sonnenberger2015-08-101-0/+29
| | | | llvm-svn: 244532
* MIR Serialization: Serialize the liveout register mask machine operands.Alex Lorenz2015-08-101-0/+43
| | | | llvm-svn: 244529
* fix minsize detection: minsize attribute implies optimizing for sizeSanjay Patel2015-08-101-0/+38
| | | | llvm-svn: 244528
* Extend late diagnostics to include late test for runtime pointer checks.Tyler Nowicki2015-08-101-1/+6
| | | | | | This patch moves checking the threshold of runtime pointer checks to the vectorization requirements (late diagnostics) and emits a diagnostic that infroms the user the loop would be vectorized if not for exceeding the pointer-check threshold. Clang will also append the options that can be used to allow vectorization. llvm-svn: 244523
* WebAssembly: print immediatesJF Bastien2015-08-101-0/+174
| | | | | | | | | | | | | | | Summary: For now output using C99's hexadecimal floating-point representation. This patch also cleans up how machine operands are printed: instead of special-casing per type of machine instruction, the code now handles operands generically. Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11914 llvm-svn: 244520
* Add support for the signx instrution alias of SPARCv9.Joerg Sonnenberger2015-08-101-0/+9
| | | | llvm-svn: 244519
* MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction.Alex Lorenz2015-08-101-0/+43
| | | | | | | | | | | | The PATCHPOINT instructions have a single optional defined register operand, but the machine verifier can't verify the optional defined register operands. This commit makes sure that the machine verifier won't report an error when a PATCHPOINT instruction doesn't have its optional defined register operand. This change will allow us to enable the machine verifier for the code generation tests for the patchpoint intrinsics. Reviewers: Juergen Ributzka llvm-svn: 244513
* [llvm-symbolizer] Remove underscores and other C mangling on WindowsReid Kleckner2015-08-105-18/+37
| | | | | | | | | | | | | | | Summary: This makes it so that reports symbolized after the fact with llvm-symbolizer are more similar to the ones we generate at runtime with in-process dbghelp. Reviewers: samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11785 llvm-svn: 244512
* StackMap: FastISel: Add an appropriate number of immediate operands to theAlex Lorenz2015-08-103-0/+60
| | | | | | | | | | | | | | | | | | frame setup instruction. This commit ensures that the stack map lowering code in FastISel adds an appropriate number of immediate operands to the frame setup instruction. The previous code added just one immediate operand, which was fine for a target like AArch64, but on X86 the ADJCALLSTACKDOWN64 instruction needs two explicit operands. This caused the machine verifier to report an error when the old code added just one. Reviewers: Juergen Ributzka Differential Revision: http://reviews.llvm.org/D11853 llvm-svn: 244508
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