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* Flip the new block-placement pass to be on by default.Chandler Carruth2012-04-1631-77/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. llvm-svn: 154816
* Remove an overly brittle test. This test will no longer be interestingChandler Carruth2012-04-161-174/+0
| | | | | | | | once we start changing the block layout, so just nuke it. If anyone has ideas about how to craft a code layout agnostic form of the test please let me know. llvm-svn: 154815
* Add a somewhat hacky heuristic to do something different from whole-loopChandler Carruth2012-04-161-5/+5
| | | | | | | | | | | | | rotation. When there is a loop backedge which is an unconditional branch, we will end up with a branch somewhere no matter what. Try placing this backedge in a fallthrough position above the loop header as that will definitely remove at least one branch from the loop iteration, where whole loop rotation may not. I haven't seen any benchmarks where this is important but loop-blocks.ll tests for it, and so this will be covered when I flip the default. llvm-svn: 154812
* Add -disassemble support for -show-inst and -show-encode capability llvm-mc. ↵Richard Barton2012-04-161-1/+1
| | | | | | | | Also refactor so all MC paraphernalia are created once for all uses as much as possible. The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use. llvm-svn: 154809
* Tweak the loop rotation logic to check whether the loop is naturallyChandler Carruth2012-04-161-2/+32
| | | | | | | | | | | laid out in a form with a fallthrough into the header and a fallthrough out of the bottom. In that case, leave the loop alone because any rotation will introduce unnecessary branches. If either side looks like it will require an explicit branch, then the rotation won't add any, do it to ensure the branch occurs outside of the loop (if possible) and maximize the benefit of the fallthrough in the bottom. llvm-svn: 154806
* Remove dead SD nodes after the combining pass. Fixes PR12201.Hal Finkel2012-04-161-0/+46
| | | | llvm-svn: 154786
* Rewrite how machine block placement handles loop rotation.Chandler Carruth2012-04-161-3/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a complex change that resulted from a great deal of experimentation with several different benchmarks. The one which proved the most useful is included as a test case, but I don't know that it captures all of the relevant changes, as I didn't have specific regression tests for each, they were more the result of reasoning about what the old algorithm would possibly do wrong. I'm also failing at the moment to craft more targeted regression tests for these changes, if anyone has ideas, it would be welcome. The first big thing broken with the old algorithm is the idea that we can take a basic block which has a loop-exiting successor and a looping successor and use the looping successor as the layout top in order to get that particular block to be the bottom of the loop after layout. This happens to work in many cases, but not in all. The second big thing broken was that we didn't try to select the exit which fell into the nearest enclosing loop (to which we exit at all). As a consequence, even if the rotation worked perfectly, it would result in one of two bad layouts. Either the bottom of the loop would get fallthrough, skipping across a nearer enclosing loop and thereby making it discontiguous, or it would be forced to take an explicit jump over the nearest enclosing loop to earch its successor. The point of the rotation is to get fallthrough, so we need it to fallthrough to the nearest loop it can. The fix to the first issue is to actually layout the loop from the loop header, and then rotate the loop such that the correct exiting edge can be a fallthrough edge. This is actually much easier than I anticipated because we can handle all the hard parts of finding a viable rotation before we do the layout. We just store that, and then rotate after layout is finished. No inner loops get split across the post-rotation backedge because we check for them when selecting the rotation. That fix exposed a latent problem with our exitting block selection -- we should allow the backedge to point into the middle of some inner-loop chain as there is no real penalty to it, the whole point is that it *won't* be a fallthrough edge. This may have blocked the rotation at all in some cases, I have no idea and no test case as I've never seen it in practice, it was just noticed by inspection. Finally, all of these fixes, and studying the loops they produce, highlighted another problem: in rotating loops like this, we sometimes fail to align the destination of these backwards jumping edges. Fix this by actually walking the backwards edges rather than relying on loopinfo. This fixes regressions on heapsort if block placement is enabled as well as lots of other cases where the previous logic would introduce an abundance of unnecessary branches into the execution. llvm-svn: 154783
* Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with ↵Craig Topper2012-04-151-16/+0
| | | | | | normal shuffle vectors. llvm-svn: 154778
* Fix PR12529. The Vxx family of instructions are only supported by AVX.Nadav Rotem2012-04-151-1/+1
| | | | | | Use non-vex instructions for SSE4. llvm-svn: 154770
* When emulating vselect using OR/AND/XOR make sure to bitcast the result back ↵Nadav Rotem2012-04-151-0/+8
| | | | | | to the original type. llvm-svn: 154764
* Added VPERM optimization for AVX2 shufflesElena Demikhovsky2012-04-151-0/+34
| | | | llvm-svn: 154761
* Rename "fpaccuracy" metadata to the more generic "fpmath". That's because I'mDuncan Sands2012-04-142-31/+31
| | | | | | | | | thinking of generalizing it to be able to specify other freedoms beyond accuracy (such as that NaN's don't have to be respected). I'd like the 3.1 release (the first one with this metadata) to have the more generic name already rather than having to auto-upgrade it in 3.2. llvm-svn: 154744
* Fix an error in BBVectorize important for vectorizing pointer types.Hal Finkel2012-04-141-0/+23
| | | | | | | | | | When vectorizing pointer types it is important to realize that potential pairs cannot be connected via the address pointer argument of a load or store. This is because even after vectorization, the address is still a scalar because the address of the higher half of the pair is implicit from the address of the lower half (it need not be, and should not be, explicitly computed). llvm-svn: 154735
* Enhance BBVectorize to more-properly handle pointer values and vectorize GEPs.Hal Finkel2012-04-141-0/+81
| | | | llvm-svn: 154734
* Fix X86 codegen for 'atomicrmw nand' to generate *x = ~(*x & y), not *x = ↵Richard Smith2012-04-131-0/+15
| | | | | | ~*x & y. llvm-svn: 154705
* Add support to BBVectorize for vectorizing selects.Hal Finkel2012-04-131-0/+30
| | | | llvm-svn: 154700
* On Darwin targets, only use vfma etc. if the source use fma() intrinsic ↵Evan Cheng2012-04-131-1/+1
| | | | | | explicitly. llvm-svn: 154689
* Consider ObjC runtime calls objc_storeWeak and others which make a copy ofDan Gohman2012-04-131-0/+131
| | | | | | | their argument as "escape" points for objc_retainBlock optimization. This fixes rdar://11229925. llvm-svn: 154682
* Catch the Python exception when subprocess.Popen is failing.Sylvestre Ledru2012-04-131-1/+6
| | | | | | | | For example, if llc cannot be found, the full python stacktrace is displayed and no interesting information are provided. + fail the process when an exception occurs llvm-svn: 154665
* Use the new Use-aware dominates method to apply the objc runtimeDan Gohman2012-04-131-0/+18
| | | | | | | library return value optimization for phi uses. Even when the phi itself is not dominated, the specific use may be dominated. llvm-svn: 154647
* Don't move objc_autorelease calls past autorelease pool boundaries whenDan Gohman2012-04-131-4/+78
| | | | | | | optimizing autorelease calls on phi nodes with null operands. This fixes rdar://11207070. llvm-svn: 154642
* Disable Hexagon test temporarily.Sirish Pande2012-04-1210-10/+20
| | | | | | | | | | | | | There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); llvm-svn: 154617
* This patch improves the MCJIT runtime dynamic loader by adding new handlingPreston Gurd2012-04-1218-18/+0
| | | | | | | | | | of zero-initialized sections, virtual sections and common symbols and preventing the loading of sections which are not required for execution such as debug information. Patch by Andy Kaylor! llvm-svn: 154610
* Fix 128-bit ptest intrinsics to take v2i64 instead of v4f32 since these are ↵Craig Topper2012-04-122-18/+18
| | | | | | integer instructions. llvm-svn: 154580
* Revert changes that were accidentally committed.Akira Hatanaka2012-04-111-2/+1
| | | | llvm-svn: 154563
* Fix string that is being checked.Akira Hatanaka2012-04-111-5/+6
| | | | llvm-svn: 154547
* Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,Akira Hatanaka2012-04-111-0/+17
| | | | | | otherwise expand FNEG during legalization. llvm-svn: 154546
* Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.Akira Hatanaka2012-04-111-0/+52
| | | | | | Invalid operation is signaled if the operand of these instructions is NaN. llvm-svn: 154545
* Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby2012-04-111-0/+13
| | | | | | of a VST instruction. llvm-svn: 154544
* Fix bugs in lowering of FCOPYSIGN nodes.Akira Hatanaka2012-04-112-43/+92
| | | | | | | | | | - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VUZP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11222366 llvm-svn: 154511
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 llvm-svn: 154505
* Add more fused mul+add/sub patterns. rdar://10139676Evan Cheng2012-04-111-16/+54
| | | | llvm-svn: 154484
* Reapply 154396 after fixing a test.Nadav Rotem2012-04-112-6/+6
| | | | | | | | | Original message: Modify the code that lowers shuffles to blends from using blendvXX to vblendXX. blendV uses a register for the selection while Vblend uses an immediate. On sandybridge they still have the same latency and execute on the same execution ports. llvm-svn: 154483
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-1/+1
| | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 llvm-svn: 154480
* Match (fneg (fma) to vfnma. rdar://10139676Evan Cheng2012-04-111-6/+25
| | | | llvm-svn: 154469
* Add retw and lretw instructions. Also, fix Intel syntax parsing for allCharles Davis2012-04-114-0/+31
| | | | | | ret instructions. llvm-svn: 154468
* Merge fma.ll into fusedMAC.llEvan Cheng2012-04-112-30/+28
| | | | llvm-svn: 154466
* Fix ARM disassembly of VLD instructions with writebacks.  And add test a caseKevin Enderby2012-04-112-0/+364
| | | | | | for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp . llvm-svn: 154459
* ARM add missing Thumb1 two-operand aliases for shift-by-immediate.Jim Grosbach2012-04-111-0/+18
| | | | | | rdar://11222742 llvm-svn: 154457
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-112-0/+87
| | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 llvm-svn: 154456
* Fix test to be register assignment invariant.Jakob Stoklund Olesen2012-04-111-1/+2
| | | | llvm-svn: 154453
* Move the constant-folding support for FP_ROUND in SelectionDAG from the ↵Owen Anderson2012-04-101-18/+2
| | | | | | | | one-operand version of getNode() to the two-operand version, since it became a two-operand node at sound point. Zap a testcase that this allows us to completely fold away. llvm-svn: 154447
* [tsan] two more compile-time optimizations:Kostya Serebryany2012-04-101-0/+61
| | | | | | | | | | | | | - don't isntrument reads from constant globals. Saves ~1.5% of instrumented instructions on CPU2006 (counting static instructions, not their execution). - don't insrument reads from vtable (which is a global constant too). Saves ~5%. I did not measure the run-time impact of this, but it is certainly non-negative. llvm-svn: 154444
* Handle llvm.fma.* intrinsics. rdar://10914096Evan Cheng2012-04-101-0/+30
| | | | llvm-svn: 154439
* Add a comment noting that the fdiv -> fmul conversion won't generateDuncan Sands2012-04-101-0/+16
| | | | | | multiplication by a denormal, and some tests checking that. llvm-svn: 154431
* Temporarily revert this patch to see if it brings the buildbots back.Eric Christopher2012-04-102-6/+6
| | | | llvm-svn: 154425
* [tsan] compile-time instrumentation: do not instrument a read ifKostya Serebryany2012-04-101-0/+32
| | | | | | | | | | | | | a write to the same temp follows in the same BB. Also add stats printing. On Spec CPU2006 this optimization saves roughly 4% of instrumented reads (which is 3% of all instrumented accesses): Writes : 161216 Reads : 446458 Reads-before-write: 18295 llvm-svn: 154418
* To ensure that we have more accurate line information for a blockEric Christopher2012-04-101-1/+2
| | | | | | | | | don't elide the branch instruction if it's the only one in the block, otherwise it's ok. PR9796 and rdar://11215207 llvm-svn: 154417
* ARM fix cc_out operand handling for t2SUBrr instructions.Jim Grosbach2012-04-101-0/+12
| | | | | | | | | | | | We were incorrectly conflating some add variants which don't have a cc_out operand with the mirroring sub encodings, which do. Part of the awesome non-orthogonality legacy of thumb1. Similarly, handling of add/sub of an immediate was sometimes incorrectly removing the cc_out operand for add/sub register variants. rdar://11216577 llvm-svn: 154411
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