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* Revert "Add Constant Hoisting Pass"Juergen Ributzka2014-01-242-57/+2
| | | | | | This reverts commit r200022 to unbreak the build bots. llvm-svn: 200024
* Add Constant Hoisting PassJuergen Ributzka2014-01-242-2/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass identifies expensive constants to hoist and coalesces them to better prepare it for SelectionDAG-based code generation. This works around the limitations of the basic-block-at-a-time approach. First it scans all instructions for integer constants and calculates its cost. If the constant can be folded into the instruction (the cost is TCC_Free) or the cost is just a simple operation (TCC_BASIC), then we don't consider it expensive and leave it alone. This is the default behavior and the default implementation of getIntImmCost will always return TCC_Free. If the cost is more than TCC_BASIC, then the integer constant can't be folded into the instruction and it might be beneficial to hoist the constant. Similar constants are coalesced to reduce register pressure and materialization code. When a constant is hoisted, it is also hidden behind a bitcast to force it to be live-out of the basic block. Otherwise the constant would be just duplicated and each basic block would have its own copy in the SelectionDAG. The SelectionDAG recognizes such constants as opaque and doesn't perform certain transformations on them, which would create a new expensive constant. This optimization is only applied to integer constants in instructions and simple (this means not nested) constant cast experessions. For example: %0 = load i64* inttoptr (i64 big_constant to i64*) Reviewed by Eric llvm-svn: 200022
* Fix known typosAlp Toker2014-01-2423-45/+45
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* InstSimplify: Make shift, select and GEP simplifications vector-aware.Benjamin Kramer2014-01-243-1/+73
| | | | llvm-svn: 200016
* Don't use "llc -filetype=obj" now that the codepath is the same.Rafael Espindola2014-01-243-3/+3
| | | | | | | r200011 remove the special codepaths in MC for inline asm, so we can now test all the logic with just llc + llvm-mc. llvm-svn: 200013
* Revert "Use DW_AT_high_pc and DW_AT_low_pc for the high and low pc for a"Eric Christopher2014-01-242-5/+3
| | | | | | | | in order to fix the cygwin/mingw bots. This reverts commit r199990. llvm-svn: 199991
* Use DW_AT_high_pc and DW_AT_low_pc for the high and low pc for aEric Christopher2014-01-242-3/+5
| | | | | | | | compile unit. Make these relocations on the platforms that need relocations and add a routine to ensure that we don't put the addresses in an offset table for split dwarf. llvm-svn: 199990
* [AArch64 NEON] Fix a bug in implementing register copy bwtween FPR16.Kevin Qin2014-01-241-1/+12
| | | | llvm-svn: 199978
* [X86] Prevent the creation of redundant ops for sadd and ssub with overflow.Juergen Ributzka2014-01-241-0/+34
| | | | | | | | | | | | | This commit teaches the X86 backend to create the same X86 instructions when it lowers an sadd/ssub with overflow intrinsic and a conditional branch that uses that overflow result. This allows SelectionDAG to recognize and remove one of the redundant operations. This fixes <rdar://problem/15874016> and <rdar://problem/15661073>. Reviewed by Nadav llvm-svn: 199976
* Implement atomicrmw operations in 32 and 64 bits for SPARCv9.Jakob Stoklund Olesen2014-01-241-1/+82
| | | | | | These all use the compare-and-swap CASA/CASXA instructions. llvm-svn: 199975
* [Sparc] Correct quad register list in the asm parser.Venkatraman Govindaraju2014-01-242-0/+12
| | | | | | Add test cases to check parsing of v9 double registers and their aliased quad registers. llvm-svn: 199974
* Make the use of DW_AT_ranges in the compile unit depend also uponEric Christopher2014-01-231-0/+96
| | | | | | the existence of comdat/special sections. llvm-svn: 199954
* Update the X86 assembler for .intel_syntax to produce an error for invalid baseKevin Enderby2014-01-231-0/+7
| | | | | | | | | registers in memory addresses that do not match the index register. As it does for .att_syntax. rdar://15887380 llvm-svn: 199948
* Update the X86 assembler for .intel_syntax to produce an error for invalidKevin Enderby2014-01-231-0/+11
| | | | | | | | | | | scale factors in memory addresses. As it does for .att_syntax. It was producing: Assertion failed: (((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) && "Invalid scale!"), function CreateMem, file /Volumes/SandBox/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp, line 1133. rdar://14967214 llvm-svn: 199942
* Replace vfmaddxx213 instructions with their 231-type equivalents in accumulatorLang Hames2014-01-231-0/+15
| | | | | | | loops. Writing back to the accumulator (231-type) allows the coalescer to eliminate an extra copy. llvm-svn: 199933
* Note the PR number.Rafael Espindola2014-01-231-0/+1
| | | | llvm-svn: 199932
* [Thumbv8] Fix the value of BLXOperandIndex of isV8EligibleForITWeiming Zhao2014-01-232-3/+23
| | | | | | | | | Originally, BLX was passed as operand #0 in MachineInstr and as operand #2 in MCInst. But now, it's operand #2 in both cases. This patch also removes unnecessary FileCheck in the test case added by r199127. llvm-svn: 199928
* Move test to x86 directory.Eric Christopher2014-01-231-0/+0
| | | | llvm-svn: 199927
* [AArch64] Added vselect patterns with float and double typesAna Pazos2014-01-231-0/+13
| | | | llvm-svn: 199925
* Avoid emitting a DWARF type attribute for an ObjC property of typeEric Christopher2014-01-231-0/+104
| | | | | | | | void. Patch by Scott Talbot. llvm-svn: 199924
* R600: Disable the BFE patternTom Stellard2014-01-231-0/+2
| | | | | | | | | | This pattern uses an SDNodeXForm, which isn't being emitted for some reason. I can get it to work by attaching the PatLeaf that has the XForm to the argument in the output pattern, but this results in an immediate being used in a register operand, which the backend can't handle yet. llvm-svn: 199918
* R600: Correctly handle vertex fetch clauses the precede ENDIFsTom Stellard2014-01-231-0/+29
| | | | | | | | The control flow finalizer would sometimes use an ALU_POP_AFTER instruction before the vetex fetch clause instead of using a POP instruction after it. llvm-svn: 199917
* R600: Unconditionally unroll loops that contain GEPs with alloca pointersTom Stellard2014-01-231-0/+37
| | | | | | | | | | | | Implement the getUnrollingPreferences() function for AMDGPUTargetTransformInfo so that loops that do address calculations on pointers derived from alloca are unconditionally unrolled. Unrolling these loops makes it more likely that SROA will be able to eliminate the allocas, which is a big win for R600 since memory allocated by alloca (private memory) is really slow. llvm-svn: 199916
* Move a unit test into the correct dir. Sorry if it broke Mips-only builds.Andrew Trick2014-01-231-0/+0
| | | | llvm-svn: 199911
* Remove tail marker when changing an argument to an alloca.Rafael Espindola2014-01-231-0/+19
| | | | | | | | | | Argument promotion can replace an argument of a call with an alloca. This requires clearing the tail marker as it is very likely that the callee is now using an alloca in the caller. This fixes pr14710. llvm-svn: 199909
* R600: Recommit 199842: Add work-around for the CF stack entry HW bugTom Stellard2014-01-231-0/+227
| | | | | | | | | | | | | | | | | | The unit test is now disabled on non-asserts builds. The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199905
* [Object][ELF][Mips] Print symbol name for MIPS ELF relocations.Simon Atanasyan2014-01-232-1/+11
| | | | llvm-svn: 199898
* AVX-512: added VPERM2D VPERM2Q VPERM2PS VPERM2PD instructions,Elena Demikhovsky2014-01-231-7/+7
| | | | | | they give better sequences than VPERMI llvm-svn: 199893
* ARM: use litpools for normal i32 imms when compiling minsize.Tim Northover2014-01-231-0/+57
| | | | | | | | | With constant-sharing, litpool loads consume 4 + N*2 bytes of code, but movw/movt pairs consume 8*N. This means litpools are better than movw/movt even with just one use. Other materialisation strategies can still be better though, so the logic is a little odd. llvm-svn: 199891
* Prevent repetitive warnings for unrecognized processors and featuresArtyom Skrobov2014-01-231-0/+15
| | | | llvm-svn: 199886
* [LPM] Make LoopSimplify no longer a LoopPass and instead both a utilityChandler Carruth2014-01-231-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | function and a FunctionPass. This has many benefits. The motivating use case was to be able to compute function analysis passes *after* running LoopSimplify (to avoid invalidating them) and then to run other passes which require LoopSimplify. Specifically passes like unrolling and vectorization are critical to wire up to BranchProbabilityInfo and BlockFrequencyInfo so that they can be profile aware. For the LoopVectorize pass the only things in the way are LoopSimplify and LCSSA. This fixes LoopSimplify and LCSSA is next on my list. There are also a bunch of other benefits of doing this: - It is now very feasible to make more passes *preserve* LoopSimplify because they can simply run it after changing a loop. Because subsequence passes can assume LoopSimplify is preserved we can reduce the runs of this pass to the times when we actually mutate a loop structure. - The new pass manager should be able to more easily support loop passes factored in this way. - We can at long, long last observe that LoopSimplify is preserved across SCEV. This *halves* the number of times we run LoopSimplify!!! Now, getting here wasn't trivial. First off, the interfaces used by LoopSimplify are all over the map regarding how analysis are updated. We end up with weird "pass" parameters as a consequence. I'll try to clean at least some of this up later -- I'll have to have it all clean for the new pass manager. Next up I discovered a really frustrating bug. LoopUnroll *claims* to preserve LoopSimplify. That's actually a lie. But the way the LoopPassManager ends up running the passes, it always ran LoopSimplify on the unrolled-into loop, rectifying this oversight before any verification could kick in and point out that in fact nothing was preserved. So I've added code to the unroller to *actually* simplify the surrounding loop when it succeeds at unrolling. The only functional change in the test suite is that we now catch a case that was previously missed because SCEV and other loop transforms see their containing loops as simplified and thus don't miss some opportunities. One test case has been converted to check that we catch this case rather than checking that we miss it but at least don't get the wrong answer. Note that I have #if-ed out all of the verification logic in LoopSimplify! This is a temporary workaround while extracting these bits from the LoopPassManager. Currently, there is no way to have a pass in the LoopPassManager which preserves LoopSimplify along with one which does not. The LPM will try to verify on each loop in the nest that LoopSimplify holds but the now-Function-pass cannot distinguish what loop is being verified and so must try to verify all of them. The inner most loop is clearly no longer simplified as there is a pass which didn't even *attempt* to preserve it. =/ Once I get LCSSA out (and maybe LoopVectorize and some other fixes) I'll be able to re-enable this check and catch any places where we are still failing to preserve LoopSimplify. If this causes problems I can back this out and try to commit *all* of this at once, but so far this seems to work and allow much more incremental progress. llvm-svn: 199884
* [AArch64]Add CHECK for two test cases testing scalar_to_vector committed in ↵Hao Liu2014-01-231-6/+19
| | | | | | r199461. llvm-svn: 199861
* [Mips] TargetStreamer Support for .set mips16.Jack Carter2014-01-221-1/+4
| | | | | | | | | | This patch updates .set mips16 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that the assembler uses for both ELF and ASCII output for these directives. llvm-svn: 199851
* Revert r162101 and replace it with a solution that works for targets where ↵Owen Anderson2014-01-221-1/+1
| | | | | | | | | | the pointer type is illegal. This is a horrible bit of code. We're calling a simplification routine *in the middle* of type legalization. We tell the simplification routine that it's running after legalization, but some of the types it will encounter will be illegal! The fix is only to invoke the simplification if the types in question were legal, so that none of its invariants will be violated. llvm-svn: 199847
* Add CHECK-LABELsMatt Arsenault2014-01-221-0/+7
| | | | llvm-svn: 199846
* Revert "R600: Add work-around for the CF stack entry HW bug"Tom Stellard2014-01-221-225/+0
| | | | | | | | | This reverts commit 35b8331cad6eb512a2506adbc394201181da94ba. The -debug-only flag for llc doesn't appear to be available in all build configurations. llvm-svn: 199845
* Provide a dummy section to fix a crash with inline assembly in LTO.Rafael Espindola2014-01-221-0/+4
| | | | | | Fixes pr18508. llvm-svn: 199843
* R600: Add work-around for the CF stack entry HW bugTom Stellard2014-01-221-0/+225
| | | | | | | | | | | | | | | | The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199842
* R600: Refactor stack size calculationTom Stellard2014-01-221-1/+1
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199840
* Handle an addrspacecast case in memcpyoptMatt Arsenault2014-01-221-0/+17
| | | | llvm-svn: 199836
* Eliminate inappropriate use of FindProgramByName() from lliAlp Toker2014-01-2214-11/+14
| | | | llvm-svn: 199835
* Add a testcase for r199430.Quentin Colombet2014-01-221-0/+4
| | | | llvm-svn: 199831
* R600: MOVA is vector onlyTom Stellard2014-01-221-1/+3
| | | | llvm-svn: 199827
* R600: Take alignment into account when calculating the stack offsetTom Stellard2014-01-221-0/+31
| | | | llvm-svn: 199826
* R600: Add support for global addresses with constant initializersTom Stellard2014-01-221-0/+41
| | | | llvm-svn: 199825
* R600: Begin private memory at the second GPR.Tom Stellard2014-01-221-0/+25
| | | | | | | This way private memory does not over-write work group information stored in GPRs 0 and 1. llvm-svn: 199824
* R600/SI: Add support for i8 and i16 private loads/storesTom Stellard2014-01-222-14/+59
| | | | llvm-svn: 199823
* Bug 18228 - Fix accepting bitcasts between vectors of pointers with aMatt Arsenault2014-01-221-0/+7
| | | | | | | | | | | | | different number of elements. Bitcasts were passing with vectors of pointers with different number of elements since the number of elements was checking SrcTy->getVectorNumElements() == SrcTy->getVectorNumElements() which isn't helpful. The addrspacecast was also wrong, but that case at least is caught by the verifier. Refactor bitcast and addrspacecast handling in castIsValid to be more readable and fix this problem. llvm-svn: 199821
* Fix inline assembly that switches between ARM and Thumb modesGreg Fitzgerald2014-01-223-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch restores the ARM mode if the user's inline assembly does not. In the object streamer, it ensures that instructions following the inline assembly are encoded correctly and that correct mapping symbols are emitted. For the asm streamer, it emits a .arm or .thumb directive. This patch does not ensure that the inline assembly contains the ADR instruction to switch modes at runtime. The problem we need to solve is code like this: int foo(int a, int b) { int r = a + b; asm volatile( ".align 2 \n" ".arm \n" "add r0,r0,r0 \n" : : "r"(r)); return r+1; } If we compile this function in thumb mode then the inline assembly will switch to arm mode. We need to make sure that we switch back to thumb mode after emitting the inline assembly or we will incorrectly encode the instructions that follow (i.e. the assembly instructions for return r+1). Based on patch by David Peixotto Change-Id: Ib57f6d2d78a22afad5de8693fba6230ff56ba48b llvm-svn: 199818
* [x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)David Woodhouse2014-01-224-9/+14
| | | | llvm-svn: 199809
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