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* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+11
| | | | llvm-svn: 129096
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-072-0/+14
| | | | | | And two test cases. llvm-svn: 129090
* While hoisting common code from if/else, hoist debug info intrinsics if they ↵Devang Patel2011-04-071-0/+53
| | | | | | match. llvm-svn: 129078
* Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal ↵Tanya Lattner2011-04-071-0/+18
| | | | | | vector type (vectors of size 3). Also included test cases. llvm-svn: 129074
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+12
| | | | | | rdar://problem/9246844 llvm-svn: 129050
* PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoadEli Friedman2011-04-073-2/+41
| | | | | | | | | | | is equivalent to any other relevant value; it isn't true in general. If it is equivalent, the LoopPromoter will tell the AST the equivalence. Also, delete the PreheaderLoad if it is unused. Chris, since you were the last one to make major changes here, can you check that this is sane? llvm-svn: 129049
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-071-0/+3
| | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 llvm-svn: 129047
* Change -arm-divmod-libcall to a target neutral option.Evan Cheng2011-04-071-1/+1
| | | | llvm-svn: 129045
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-0/+11
| | | | | | rdar://problem/9246650 llvm-svn: 129042
* Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ↵Owen Anderson2011-04-061-0/+9
| | | | | | folded comparisons, just like ADD and SUB. llvm-svn: 129038
* A8.6.393Johnny Chen2011-04-061-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ llvm-svn: 129033
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-063-0/+16
| | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-061-0/+3
| | | | | | | | | Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 llvm-svn: 129015
* This testcase passed even without the fix. Added the target info to make theNadav Rotem2011-04-061-0/+3
| | | | | | test fail (without the fix). Thanks Dan. llvm-svn: 128999
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-1/+4
| | | | | | | | | | Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 llvm-svn: 128977
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for ↵Johnny Chen2011-04-051-3/+6
| | | | | | | | | | illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 llvm-svn: 128958
* A7.3 register encodingJohnny Chen2011-04-052-1/+11
| | | | | | | | | | | | | Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 llvm-svn: 128949
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-051-0/+9
| | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 llvm-svn: 128945
* remove postdom frontiers, because it is dead. Forward dom frontiers areChris Lattner2011-04-053-817/+0
| | | | | | still used by RegionInfo :( llvm-svn: 128943
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-051-0/+9
| | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941
* These tests no longer require linear scan because reserved register ↵Jakob Stoklund Olesen2011-04-055-19/+14
| | | | | | coalescing is now universal. llvm-svn: 128936
* Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.Jakob Stoklund Olesen2011-04-059-1/+10
| | | | llvm-svn: 128935
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-051-0/+3
| | | | | | | | Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change. rdar://problem/9236873 llvm-svn: 128922
* Fix one more batch of X86 tests to be register allocation dependent.Jakob Stoklund Olesen2011-04-059-2797/+2811
| | | | llvm-svn: 128919
* When dead code elimination removes all but one use, try to fold the single ↵Jakob Stoklund Olesen2011-04-051-0/+1
| | | | | | | | def into the remaining use. Rematerialization can leave single-use loads behind that we might as well fold whenever possible. llvm-svn: 128918
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-052-4/+5
| | | | llvm-svn: 128913
* LDRD now prints out two dst registers.Johnny Chen2011-04-051-1/+1
| | | | llvm-svn: 128909
* Fix test-llvm failures.Johnny Chen2011-04-056-13/+13
| | | | llvm-svn: 128906
* Constants with multiple encodings (ARM):Johnny Chen2011-04-052-6/+6
| | | | | | | | | | An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. llvm-svn: 128897
* Check for invalid register encodings for UMAAL and friends where:Johnny Chen2011-04-051-0/+11
| | | | | | | | | if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; if dHi == dLo then UNPREDICTABLE; rdar://problem/9230202 llvm-svn: 128895
* ARM doesn't support byval yet. XFAIL this test until it does.Stuart Hastings2011-04-051-0/+1
| | | | llvm-svn: 128891
* Ensure all defs referring to a virtual register are marked dead by ↵Jakob Stoklund Olesen2011-04-051-1/+5
| | | | | | | | | | | | addRegisterDead(). There can be multiple defs for a single virtual register when they are defining sub-registers. The missing <dead> flag was stopping the inline spiller from eliminating dead code after rematerialization. llvm-svn: 128888
* Print visibility info for external variables.Rafael Espindola2011-04-051-2/+5
| | | | llvm-svn: 128887
* InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away addressNadav Rotem2011-04-051-0/+16
| | | | | | | space info. We crash with an assert in this case. This change checks that the address space of the bitcasted pointer is the same as the gep ptr. llvm-svn: 128884
* Fix up testcase for previous commit.Eric Christopher2011-04-051-1/+1
| | | | llvm-svn: 128870
* Fix register-dependent X86 tests.Jakob Stoklund Olesen2011-04-0530-76/+96
| | | | llvm-svn: 128867
* Fix SRS/SRSW encoding bits.Johnny Chen2011-04-052-0/+24
| | | | | | | | | rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with http://llvm.org/viewvc/llvm-project?view=rev&revision=128859. llvm-svn: 128864
* Allow coalescing with reserved physregs in certain cases:Jakob Stoklund Olesen2011-04-042-112/+0
| | | | | | | | | | | | | | | | | | | | | | | | | When a virtual register has a single value that is defined as a copy of a reserved register, permit that copy to be joined. These virtual register are usually copies of the stack pointer: %vreg75<def> = COPY %ESP; GR32:%vreg75 MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill> MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0 MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0 CALLpcrel32 ... Coalescing these virtual registers early decreases register pressure. Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after register allocation was completed. The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail because it depends on linear scan spilling a particular register. I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of instructions emitted, and its revision history shows the 'correct' count being edited many times. llvm-svn: 128845
* Fix incorrect alignment for NEON VST2b32_UPD.Johnny Chen2011-04-041-0/+3
| | | | | | rdar://problem/9225433 llvm-svn: 128841
* Disable the PowerPC/Atomics-64 test.Jakob Stoklund Olesen2011-04-041-2/+8
| | | | | | | | The code inserted by PPCTargetLowering::EmitInstrWithCustomInserter for ppc64 is wrong, and I don't know how to fix it. It seems to be using the correct register classes for pointers, but it inserts all 32-bit instructions. llvm-svn: 128835
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-041-0/+18
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Fix PowerPC tests to be register allocator independent.Jakob Stoklund Olesen2011-04-042-8/+8
| | | | llvm-svn: 128827
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-0/+53
| | | | llvm-svn: 128826
* Remove some support for ReturnInsts with multiple operands, and forJay Foad2011-04-041-6/+0
| | | | | | | returning a scalar value in a function whose return type is a single- element structure or array. llvm-svn: 128810
* PR9446: RecursivelyDeleteTriviallyDeadInstructions can delete the instructionEli Friedman2011-04-021-0/+32
| | | | | | | | | | | after the given instruction; make sure to handle that case correctly. (It's difficult to trigger; the included testcase involves a dead block, but I don't think that's a requirement.) While I'm here, get rid of the unnecessary warning about SimplifyInstructionsInBlock, since it should work correctly as far as I know. llvm-svn: 128782
* ptx: support setp's 4-operand formatChe-Liang Chiou2011-04-021-0/+25
| | | | llvm-svn: 128767
* Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich2011-04-021-0/+11
| | | | | | | | registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. llvm-svn: 128759
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-021-0/+3
| | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 llvm-svn: 128757
* Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.Johnny Chen2011-04-011-0/+13
| | | | | | rdar://problem/9224276 llvm-svn: 128749
* MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is ↵Johnny Chen2011-04-011-0/+17
| | | | | | | | UNPREDICTABLE. rdar://problem/9224120 llvm-svn: 128748
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