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| author | Tanya Lattner <tonic@nondot.org> | 2011-04-07 15:24:20 +0000 |
|---|---|---|
| committer | Tanya Lattner <tonic@nondot.org> | 2011-04-07 15:24:20 +0000 |
| commit | 266792a55a16d69920daf71310e93db49004befc (patch) | |
| tree | 5629c54fef25265f4eab242b020e03bb0efc4af0 /llvm/test | |
| parent | 65bef04ea7ca55ae26b2fa0d42b5458a1e36c924 (diff) | |
| download | bcm5719-llvm-266792a55a16d69920daf71310e93db49004befc.tar.gz bcm5719-llvm-266792a55a16d69920daf71310e93db49004befc.zip | |
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
llvm-svn: 129074
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/ARM/vector-DAGCombine.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll index 3ab0cfcbbc7..81bdc44863b 100644 --- a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll @@ -105,3 +105,21 @@ define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind { store i64 %t1, i64* %ptr ret void } + +; Test trying to do a AND Combine on illegal types. +define void @andVec(<3 x i8>* %A) nounwind { + %tmp = load <3 x i8>* %A, align 4 + %and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7> + store <3 x i8> %and, <3 x i8>* %A + ret void +} + + +; Test trying to do an OR Combine on illegal types. +define void @orVec(<3 x i8>* %A) nounwind { + %tmp = load <3 x i8>* %A, align 4 + %or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7> + store <3 x i8> %or, <3 x i8>* %A + ret void +} + |
