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* [MergeIcmps] Add the test case from PR36557.Clement Courbet2018-03-021-0/+160
| | | | | | | | | | Summary: See PR36557. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44009 llvm-svn: 326574
* Revert "[WebAssembly] More uses of uint8_t" and "[WebAssembly] Update tests"Nicholas Wilson2018-03-021-9/+9
| | | | | | | | | | This reverts commits r326541 and r326571. The tests were correct, and were updated with incorrect expectations. The original commit was broken and should be reverted to get things back to a working state. llvm-svn: 326572
* [WebAssembly] Update tests after r326541Ilya Biryukov2018-03-021-9/+9
| | | | | | | | | | r326541 slightly increased the size of WebAssembly object files and it broke test/MC/WebAssembly/global-ctor-dtor.ll. This commit updates the test to unbreak it, also mentioned this to the author of the original commit in case they don't want it. llvm-svn: 326571
* [ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WBFlorian Hahn2018-03-024-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code generation of VLD3, VLD4, VST3 and VST4 with register writeback is broken due to 2 separate bugs: 1) VLD1d64TPseudoWB_register and VLD1d64QPseudoWB_register are missing rules to expand them to non pseudo MIR. These are selected for ARMISD::VLD3_UPD/VLD4_UPD with v1i64 vectors in SelectVLD. 2) Selection of the right VLD/VST instruction is broken for load and store of 3 and 4 v1i64 vectors. SelectVLD and SelectVST are called with MIR opcode for fixed writeback (ie increment is access size) and call getVLDSTRegisterUpdateOpcode() to select an opcode with register writeback if base register update is of a different size. Since getVLDSTRegisterUpdateOpcode() only knows about VLD1/VLD2/VST1/VST2 the call is currently conditional on the number of element in the vector. However, VLD1/VST1 is selected by SelectVLD/SelectVST's caller for load and stores of 3 or 4 v1i64 vectors. Therefore the opcode is not updated which later lead to a fixed writeback instruction being constructed with an extra operand for the register writeback. This patch addresses the two issues as follows: - it adds the necessary mapping from VLD1d64TPseudoWB_register and VLD1d64QPseudoWB_register to VLD1d64Twb_register and VLD1d64Qwb_register respectively. Like for the existing _fixed variants, the cost of these is bumped for unaligned access. - it changes the logic in SelectVLD and SelectVSD to call isVLDfixed and isVSTfixed respectively to decide whether the opcode should be updated. It also reworks the logic and comments for pushing the writeback offset operand and r0 operand to clarify the logic: writeback offset needs to be pushed if it's a register writeback, r0 needs to be pushed if not and the instruction is a VLD1/VLD2/VST1/VST2. Reviewers: rengolin, t.p.northover, samparker Reviewed By: samparker Patch by Thomas Preud'homme <thomas.preudhomme@arm.com> Differential Revision: https://reviews.llvm.org/D42970 llvm-svn: 326570
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnumMatt Arsenault2018-03-021-0/+66
| | | | | | Patch by Tom Stellard llvm-svn: 326567
* [ThinLTO] Added a couple of C LTO API interfaces to control the cache policy.Ekaterina Romanova2018-03-021-0/+34
| | | | | | | | | | - thinlto_codegen_set_cache_size_bytes to control the absolute size of cache directory. - thinlto_codegen_set_cache_size_files the size and amount of files in cache directory. These functions have been supported in C++ LTO API for a long time, but were absent in C LTO API. Differential Revision: https://reviews.llvm.org/D42446 llvm-svn: 326537
* AMDGPU/GCN: Promote i16 ctpopJan Vesely2018-03-021-0/+334
| | | | | | | | | i16 capable ASICs do not support i16 operands for this instruction. Add tablegen pattern to merge chained i16 additions. Differential Revision: https://reviews.llvm.org/D43985 llvm-svn: 326535
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSIMatt Arsenault2018-03-021-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326534
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUIMatt Arsenault2018-03-021-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326533
* AMDGPU/GlobalISel: Define instruction mapping for G_FMULMatt Arsenault2018-03-021-0/+69
| | | | llvm-svn: 326532
* [InstCombine] Add more test case to fpextend.ll.Craig Topper2018-03-021-0/+186
| | | | | | This includes the test cases from D43970 and additional tests for combining (fptrunc (binop (fpext), (fpext))) where the pre-extended types don't match the trunc and therefore can't be completely removed. llvm-svn: 326528
* AMDGPU/GlobalISel: Define instruction mapping for G_FADDMatt Arsenault2018-03-021-0/+69
| | | | | | Patch by Tom Stellard llvm-svn: 326526
* AMDGPU/GlobalISel: Define instruction mapping for G_SHLMatt Arsenault2018-03-021-0/+68
| | | | | | Patch by Tom Stellard llvm-svn: 326525
* AMDGPU/GlobalISel: Define instruction mapping for G_XORMatt Arsenault2018-03-021-0/+68
| | | | llvm-svn: 326524
* AMDGPU/GlobalISel: Define instruction mapping for G_ANDMatt Arsenault2018-03-021-0/+68
| | | | | | Patch by Tom Stellard llvm-svn: 326523
* [ArgumentPromotion] don't break musttail invariant PR36543Fedor Indutny2018-03-021-0/+45
| | | | | | | | | | | | | | | | Summary: Do not break musttail invariant by promoting arguments of musttail callee or caller. Reviewers: sanjoy, dberlin, hfinkel, george.burgess.iv, fhahn, rnk Reviewed By: rnk Subscribers: rnk, llvm-commits Differential Revision: https://reviews.llvm.org/D43926 llvm-svn: 326521
* [InstCombine] Simplify test cases by removing loads/stores that aren't ↵Craig Topper2018-03-021-72/+40
| | | | | | | | required for what is being tested. The loads and stores were getting the data and storing the results. There's no reason we can't just use function arguments and return. llvm-svn: 326515
* [InstCombine] allow fmul fold with less than 'fast'Sanjay Patel2018-03-022-13/+14
| | | | | | | | | | | | | | | | | | This is a retry of r326502 with updates to the reassociate test file that I missed the first time. @test15_reassoc in the supposed -reassociate test file (except that it tests 2 other passes too...) shows that there's no clear responsiblity for reassociation transforms. Instcombine now gets that case, but only because the constant values are identical. Otherwise, it would still miss that pattern. Reassociate doesn't get that case because it hasn't been updated to use less than 'fast' FMF. llvm-svn: 326513
* [Reassociate] regenerate checks; NFCSanjay Patel2018-03-011-61/+62
| | | | llvm-svn: 326511
* revert r326502: [InstCombine] allow fmul fold with less than 'fast'Sanjay Patel2018-03-011-13/+11
| | | | | | | | I forgot that I added tests for 'reassoc' to -reassociate, but suprisingly that file calls -instcombine too, so it is affected. I'll update that file and try again. llvm-svn: 326510
* [InstCombine] allow fmul fold with less than 'fast'Sanjay Patel2018-03-011-11/+13
| | | | llvm-svn: 326502
* [DAGCombiner] When combining zero_extend of a truncate, only mask before ↵Craig Topper2018-03-0116-91/+69
| | | | | | | | | | extending for vectors. Masking first, prevents the extend from being combine with loads. Its also interfering with some vXi1 extraction code. Differential Revision: https://reviews.llvm.org/D42679 llvm-svn: 326500
* [X86][MMX] Improve handling of 64-bit MMX constantsSimon Pilgrim2018-03-012-24/+4
| | | | | | | | | | | | 64-bit MMX constant generation usually ends up lowering into SSE instructions before being spilled/reloaded as a MMX type. This patch bitcasts the constant to a double value to allow correct loading directly to the MMX register. I've added MMX constant asm comment support to improve testing, it's better to always print the double values as hex constants as MMX is mainly an integer unit (and even with 3DNow! its just floats). Differential Revision: https://reviews.llvm.org/D43616 llvm-svn: 326497
* [SelectionDAG] Support some SimplifySetCC cases for comparing against vector ↵Craig Topper2018-03-012-50/+30
| | | | | | | | | | | | | | splats of constants. This supports things like (setcc ugt X, 0) -> (setcc ne X, 0) I've restricted to only make changes to vectors before legalize ops because I doubt all targets have accurate condition code legality information for vectors given how little we did before. Differential Revision: https://reviews.llvm.org/D42948 llvm-svn: 326495
* [X86][AVX] Add v2f32 <-> v2i8/v2i16/v2i32 vector testsSimon Pilgrim2018-03-011-0/+342
| | | | llvm-svn: 326494
* [Hexagon] Add trap1 instructionKrzysztof Parzyszek2018-03-012-1/+13
| | | | llvm-svn: 326492
* Add an llc testcase analogous to test/LTO/X86/strip-debug-info.llAdrian Prantl2018-03-011-0/+22
| | | | | | rdar://problem/37963669 llvm-svn: 326491
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtzMatt Arsenault2018-03-011-0/+66
| | | | | | Patch by Tom Stellard llvm-svn: 326490
* AMDGPU/GlobalISel: Define instruction mapping for G_ORMatt Arsenault2018-03-011-0/+68
| | | | | | Patch by Tom Stellard llvm-svn: 326489
* [X86][SSE] Regenerate float to/from i8/i16 vector testsSimon Pilgrim2018-03-011-20/+238
| | | | llvm-svn: 326488
* [X86][SSE] Regenerate odd sized sext/zext testsSimon Pilgrim2018-03-011-10/+158
| | | | llvm-svn: 326484
* AMDGPU/GlobalISel: Define instruction mapping for G_BITCASTMatt Arsenault2018-03-011-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326482
* AMDGPU/GlobalISel: Mark i32->i64 zext as legalMatt Arsenault2018-03-011-0/+14
| | | | llvm-svn: 326481
* [AArch64] Add support for secrel add/load/store relocations for COFFMartin Storsjo2018-03-011-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D43288 llvm-svn: 326480
* AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.comprMatt Arsenault2018-03-011-0/+67
| | | | | | Patch by Tom Stellard llvm-svn: 326479
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.expMatt Arsenault2018-03-011-0/+77
| | | | | | Patch by Tom Stellard llvm-svn: 326477
* [InstCombine] Auto-generate complete checks. NFCCraig Topper2018-03-011-141/+246
| | | | llvm-svn: 326474
* AMDGPU/GlobalISel: Define InstrMappings for G_ICMPMatt Arsenault2018-03-011-0/+67
| | | | | | Patch by Tom Stellard llvm-svn: 326472
* AMDGPU/GlobalISel: Make i32 mul legalMatt Arsenault2018-03-011-0/+18
| | | | llvm-svn: 326471
* AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEFMatt Arsenault2018-03-011-6/+27
| | | | | | Patch by Tom Stellard llvm-svn: 326470
* AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANTMatt Arsenault2018-03-011-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326468
* AMDGPU/GlobalISel: Make i32 xor legalMatt Arsenault2018-03-011-0/+18
| | | | llvm-svn: 326466
* AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legalMatt Arsenault2018-03-011-0/+35
| | | | | | Patch by Tom Stellard llvm-svn: 326465
* AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legalMatt Arsenault2018-03-011-0/+14
| | | | | | Patch by Tom Stellard llvm-svn: 326464
* [Hexagon] Add guest registersKrzysztof Parzyszek2018-03-011-0/+67
| | | | llvm-svn: 326450
* [InstCombine] remove stale comments for tests; NFCSanjay Patel2018-03-011-3/+0
| | | | llvm-svn: 326448
* [WebAssembly] Update pre-generated test files to match latest llc output. NFC.Nicholas Wilson2018-03-0110-29/+29
| | | | | | | | The ordering of llc's output was changed in rL326334. Differential Revision: https://reviews.llvm.org/D43941 llvm-svn: 326445
* [AArch64] generate vuzp instead of movSebastian Pop2018-03-011-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when a BUILD_VECTOR is created out of a sequence of EXTRACT_VECTOR_ELT with a specific pattern sequence, either <0, 2, 4, ...> or <1, 3, 5, ...>, replace the BUILD_VECTOR with either vuzp1 or vuzp2. With this patch LLVM generates the following code for the first function fun1 in the testcase: adrp x8, .LCPI0_0 ldr q0, [x8, :lo12:.LCPI0_0] tbl v0.16b, { v0.16b }, v0.16b ext v1.16b, v0.16b, v0.16b, #8 uzp1 v0.8b, v0.8b, v1.8b str d0, [x8] ret Without this patch LLVM currently generates this code: adrp x8, .LCPI0_0 ldr q0, [x8, :lo12:.LCPI0_0] tbl v0.16b, { v0.16b }, v0.16b mov v1.16b, v0.16b mov v1.b[1], v0.b[2] mov v1.b[2], v0.b[4] mov v1.b[3], v0.b[6] mov v1.b[4], v0.b[8] mov v1.b[5], v0.b[10] mov v1.b[6], v0.b[12] mov v1.b[7], v0.b[14] str d1, [x8] ret llvm-svn: 326443
* [InstCombine] move/add tests for fmul reassociation; NFCSanjay Patel2018-03-012-12/+72
| | | | | | | This transform may be out-of-scope for instcombine, but this is only documenting the current behavior. llvm-svn: 326442
* [InstCombine] auto-generate full checks; NFCSanjay Patel2018-03-011-51/+49
| | | | llvm-svn: 326440
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