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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 02:19:11 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-03-02 02:19:11 +0000 |
| commit | b23041ad4d3a5a045fad0be10e6aa15db135f91a (patch) | |
| tree | c6d240f3b92350dd7f7796d409ec568d8c6bee50 /llvm/test | |
| parent | 327d5fb2e5f434b36f7c8bbff45169662b4ff683 (diff) | |
| download | bcm5719-llvm-b23041ad4d3a5a045fad0be10e6aa15db135f91a.tar.gz bcm5719-llvm-b23041ad4d3a5a045fad0be10e6aa15db135f91a.zip | |
AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUI
Patch by Tom Stellard
llvm-svn: 326533
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir new file mode 100644 index 00000000000..0f5f268e32e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir @@ -0,0 +1,31 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s + +--- +name: fptoui_s +legalized: true + +body: | + bb.0: + liveins: $sgpr0 + ; CHECK-LABEL: name: fptoui_s + ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; CHECK: [[FPTOUI:%[0-9]+]]:vgpr(s32) = G_FPTOUI [[COPY]](s32) + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = G_FPTOUI %0 +... + +--- +name: fptoui_v +legalized: true + +body: | + bb.0: + liveins: $vgpr0 + ; CHECK-LABEL: name: fptoui_v + ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK: [[FPTOUI:%[0-9]+]]:vgpr(s32) = G_FPTOUI [[COPY]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_FPTOUI %0 +... |
