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* [InstCombine] Add test cases for BITWISE_OP( BSWAP(x), CONSTANT ) -> BSWAP( ↵Craig Topper2017-07-031-0/+33
| | | | | | BITWISE_OP(x, BSWAP(CONSTANT) ) ) with splat vectors. NFC llvm-svn: 307001
* [InstCombine] Support BITWISE_OP(BSWAP(A),BSWAP(B))->BSWAP(BITWISE_OP(A, B)) ↵Craig Topper2017-07-031-12/+9
| | | | | | for vectors. llvm-svn: 306999
* [InstCombine] Add test cases showing missed opportunity to fold ↵Craig Topper2017-07-031-0/+40
| | | | | | BITWISE_OP(BSWAP(A),BSWAP(B))->BSWAP(BITWISE_OP(A, B)) for vectors. NFC llvm-svn: 306998
* AMDGPU: Add operand target flags serializationMatt Arsenault2017-07-021-0/+29
| | | | llvm-svn: 306995
* [X86][AVX512] Test AVX512VPOPCNTDQ CTPOP with/without AVX512BWSimon Pilgrim2017-07-021-29/+57
| | | | llvm-svn: 306991
* [X86][AVX512VPOPCNTDQ] Improve support for v16i8/v8i16/v16i16/ CTPOPSimon Pilgrim2017-07-026-156/+111
| | | | | | Zero extend to v16i32/v8i64, use VPOPCNTDQ instructions and truncate back. llvm-svn: 306990
* [X86][AVX512] Cleanup tzcnt tests triples and attributesSimon Pilgrim2017-07-021-36/+36
| | | | | | Avoid use of specific -mcpu llvm-svn: 306989
* [X86][AVX512] Cleanup popcnt tests triples and attributesSimon Pilgrim2017-07-021-15/+15
| | | | | | Avoid use of specific -mcpu llvm-svn: 306988
* [InstCombine] fix crash when folding cmp+bswap vectorSanjay Patel2017-07-022-30/+36
| | | | | | | | | We assumed the constant was a scalar when creating the replacement operand. Also, improve tests for this fold and move the tests for this fold to their own file. I'll move the related and missing tests to this file as a follow-up. llvm-svn: 306985
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-024-72/+126
| | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. llvm-svn: 306984
* [x86] remove unnecessary RUN for test after auto-generating checks; NFCSanjay Patel2017-07-021-5/+21
| | | | llvm-svn: 306983
* [x86] update test to use FileCheck and auto-generate checks; NFCSanjay Patel2017-07-021-1/+50
| | | | llvm-svn: 306982
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-024-32/+41
| | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. llvm-svn: 306981
* [InstCombine] look through bswap/bitreverse for equality comparisonsSanjay Patel2017-07-021-12/+4
| | | | | | | | | I noticed this missed bswap optimization in the CGP memcmp() expansion, and then I saw that we don't have the fold in InstCombine. Differential Revision: https://reviews.llvm.org/D34763 llvm-svn: 306980
* llvm/test/Transforms/LoopVectorize/X86/slm-no-vectorize.ll: -debug is ↵NAKAMURA Takumi2017-07-021-0/+1
| | | | | | available in +Asserts. llvm-svn: 306979
* [X86][SSE] Attempt to combine 64-bit and 32-bit shuffles to unary shuffles ↵Simon Pilgrim2017-07-022-2/+2
| | | | | | | | before bit shifts We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive llvm-svn: 306978
* [X86][SSE] Attempt to combine 64-bit and 16-bit shuffles to unary shuffles ↵Simon Pilgrim2017-07-021-5/+2
| | | | | | | | | | before bit shifts We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive The 32-bit shuffles are a bit tricky and will be dealt with in a later patch llvm-svn: 306977
* [X86][SSE] Add test showing missed opportunity to combine to pshuflwSimon Pilgrim2017-07-021-0/+18
| | | | | | We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive llvm-svn: 306976
* [X86][CM] update add\sub costs of vectors of 64 in X86\SLM archMohammed Agabaria2017-07-022-7/+69
| | | | | | | | | this patch updates the cost of addq\subq (add\subtract of vectors of 64bits) based on the performance numbers of SLM arch. Differential Revision: https://reviews.llvm.org/D33983 llvm-svn: 306974
* [X86] Rerun "update_llc_test_checks" tool on CodeGen tests. NFC.Gadi Haber2017-07-023-0/+75
| | | | | | | | | | This is NFC after rerunning the "update_llc_test_checks.py" tool on the CodeGen X86 tests in order to submit a patch. Minor differences due to added "End of Function" lines. Reviewers: zvi Differential Revision: https://reviews.llvm.org/D34933 llvm-svn: 306973
* [GlobalISel][X86] Support G_GLOBAL_VALUE operation.Igor Breger2017-07-024-0/+220
| | | | | | | | | | | | | | | | | Summary: Support G_GLOBAL_VALUE operation. For now most of the PIC configurations not implemented yet. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34738 Conflicts: test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir llvm-svn: 306972
* [GlobalISel][X86] Support vector type G_UNMERGE_VALUES selection.Igor Breger2017-07-023-17/+283
| | | | | | | | | | | | | | | | Summary: Support vector type G_UNMERGE_VALUES selection. For now G_UNMERGE_VALUES marked as legal for any type, so nothing to do in legalizer. Reviewers: t.p.northover, qcolombet, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33665 llvm-svn: 306971
* fix trivial typos; NFCHiroshi Inoue2017-07-021-1/+1
| | | | | | suport -> support llvm-svn: 306968
* [InstCombine] Fold (a | b) ^ (~a | ~b) --> ~(a ^ b) and (a & b) ^ (~a & ~b) ↵Craig Topper2017-07-022-32/+16
| | | | | | | | | | | | | | | | | | | --> ~(a ^ b) Summary: I came across this while thinking about what would happen if one of the operands in this xor pattern was itself a inverted (A & ~B) ^ (~A & B)-> (A^B). The patterns here assume that the (~a | ~b) will be demorganed to ~(a & b) first. Though I wonder if there's a multiple use case that would prevent the demorgan. Reviewers: spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34870 llvm-svn: 306967
* [X86][RDSEED] Split off i64 intrinsic tests and test i16/i32 on 32-bit ↵Simon Pilgrim2017-07-012-29/+56
| | | | | | target as well. llvm-svn: 306961
* [X86][RDRAND] Split off i64 intrinsic tests and test i16/i32 on 32-bit ↵Simon Pilgrim2017-07-012-36/+102
| | | | | | target as well. llvm-svn: 306960
* [X86] Removed reference to update_test_checks.pySimon Pilgrim2017-07-011-1/+1
| | | | llvm-svn: 306959
* [X86][AVX] Remove duplicate autogeneration noteSimon Pilgrim2017-07-011-3/+2
| | | | llvm-svn: 306958
* fix trivial typos, NFCHiroshi Inoue2017-07-011-2/+2
| | | | llvm-svn: 306952
* [AVR] Remove a bunch of now-obselete testsDylan McKay2017-07-014-20/+0
| | | | | | The fixups in these instructions are now lowered into relocations. llvm-svn: 306947
* Remove the default ARMSubtarget from the ARM TargetMachine.Eric Christopher2017-07-011-10/+0
| | | | | | | This enables us to ensure better LTO and code generation in the face of module linking. Remove a report_fatal_error from the TargetMachine and replace it with an assert in ARMSubtarget - and remove the test that depended on the error. The assertion will still fire in the case that we were reporting before, but error reporting needs to be in front end tools if possible for options parsing. llvm-svn: 306939
* [Cloner] Re-map simplfied cloned instructions.Davide Italiano2017-07-011-0/+25
| | | | | | | | | | | | | | | This commit pretty much rolls back the logic added in r306495 as in the testcase provided we simplify an `icmp` looking through a PHI that hasn't been mapped yet. I think instsimplify shouldn't do threading over select/phis or just looking through phis in general, but this is what we have now. Also, add a test to prevent this from happening in case somebody wants to modify this code again. Briefly discussed with Kyle Butt (thanks Kyle!). llvm-svn: 306938
* Recommit "r306541 - Add zero-length check to memcpy/memset load store loop ↵Teresa Johnson2017-07-011-0/+4
| | | | | | | | | | expansion"" With fix for use-after-free errors. We can't add the new branch and remove the old one until we are done with the Builder constructed for the block. llvm-svn: 306937
* Revert "r306473 - re-commit r306336: Enable vectorizer-maximize-bandwidth by ↵Teresa Johnson2017-07-0111-76/+67
| | | | | | | | | default." This still breaks PPC tests we have. I'll forward reproduction instructions to dehao. llvm-svn: 306936
* re-commit r306336: Enable vectorizer-maximize-bandwidth by default.Teresa Johnson2017-07-0111-67/+76
| | | | | | Differential Revision: https://reviews.llvm.org/D33341 llvm-svn: 306935
* revert r306336 for breaking ppc test.Teresa Johnson2017-07-0111-76/+67
| | | | llvm-svn: 306934
* Enable vectorizer-maximize-bandwidth by default.Teresa Johnson2017-07-0111-67/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: vectorizer-maximize-bandwidth is generally useful in terms of performance. I've tested the impact of changing this to default on speccpu benchmarks on sandybridge machines. The result shows non-negative impact: spec/2006/fp/C++/444.namd 26.84 -0.31% spec/2006/fp/C++/447.dealII 46.19 +0.89% spec/2006/fp/C++/450.soplex 42.92 -0.44% spec/2006/fp/C++/453.povray 38.57 -2.25% spec/2006/fp/C/433.milc 24.54 -0.76% spec/2006/fp/C/470.lbm 41.08 +0.26% spec/2006/fp/C/482.sphinx3 47.58 -0.99% spec/2006/int/C++/471.omnetpp 22.06 +1.87% spec/2006/int/C++/473.astar 22.65 -0.12% spec/2006/int/C++/483.xalancbmk 33.69 +4.97% spec/2006/int/C/400.perlbench 33.43 +1.70% spec/2006/int/C/401.bzip2 23.02 -0.19% spec/2006/int/C/403.gcc 32.57 -0.43% spec/2006/int/C/429.mcf 40.35 +0.27% spec/2006/int/C/445.gobmk 26.96 +0.06% spec/2006/int/C/456.hmmer 24.4 +0.19% spec/2006/int/C/458.sjeng 27.91 -0.08% spec/2006/int/C/462.libquantum 57.47 -0.20% spec/2006/int/C/464.h264ref 46.52 +1.35% geometric mean +0.29% The regression on 453.povray seems real, but is due to secondary effects as all hot functions are bit-identical with and without the flag. I started this patch to consult upstream opinions on this. It will be greatly appreciated if the community can help test the performance impact of this change on other architectures so that we can decided if this should be target-dependent. Reviewers: hfinkel, mkuper, davidxl, chandlerc Reviewed By: chandlerc Subscribers: rengolin, sanjoy, javed.absar, bjope, dorit, magabari, RKSimon, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D33341 llvm-svn: 306933
* Rewrite ARM execute only support to avoid the use of a command line flag and ↵Eric Christopher2017-07-014-15/+15
| | | | | | | | unqualified ARMSubtarget lookup. Paired with a clang commit to use the new behavior. llvm-svn: 306927
* [ORE] Add diagnostics hotness thresholdBrian Gesiak2017-06-302-1/+44
| | | | | | | | | | | | | | | | | | | | Summary: Add an option to prevent diagnostics that do not meet a minimum hotness threshold from being output. When generating optimization remarks for large codebases with a ton of cold code paths, this option can be used to limit the optimization remark output at a reasonable size. Discussion of this change can be read here: http://lists.llvm.org/pipermail/llvm-dev/2017-June/114377.html Reviewers: anemet, davidxl, hfinkel Reviewed By: anemet Subscribers: qcolombet, javed.absar, fhahn, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D34867 llvm-svn: 306912
* [llvm-pdbutil] Output the symbol offset when dumping.Zachary Turner2017-06-301-50/+50
| | | | | | | | | | | | | | | | Type records have a unique type index, but symbol records do not. Instead, symbol records refer to other symbol records by referencing their offset in the symbol stream. In a sense this is the analogue of the TypeIndex, but we are not printing it in the dumper. Printing it not only gives us more useful information when manually investigating the contents of a PDB, but also allows us to write better tests by enabling us to verify that fields that reference other symbol records do so correctly. Differential Revision: https://reviews.llvm.org/D34906 llvm-svn: 306890
* [codeview] Use the first valid source location at the top of every MBBReid Kleckner2017-06-302-1/+98
| | | | | | | | | | | | | | | | If the instructions at the beginning of the block have no location, we're better off using the location of the first instruction in the current basic block. At the very least, that instruction post-dominates this one, whereas if we don't emit a .cv_loc directive, we end up using the potentially invalid location that falls through from the previous block. We could probably do better here by emitting some kind of ".cv_loc end" directive that stops the line table entry of the previous .cv_loc directive from bleeding out of its basic block. This would improve the line table when an entire MBB has no valid location info. llvm-svn: 306889
* [Hexagon] Implement frame pointer elimination with -fomit-frame-pointerKrzysztof Parzyszek2017-06-303-24/+92
| | | | | | | It applies to leaf functions that are otherwise not required to have a frame pointer. llvm-svn: 306888
* [LV] Sink casts to unravel first order recurrenceAyal Zaks2017-06-301-0/+80
| | | | | | | | | | | Check if a single cast is preventing handling a first-order-recurrence Phi, because the scheduling constraints it imposes on the first-order-recurrence shuffle are infeasible; but they can be made feasible by moving the cast downwards. Record such casts and move them when vectorizing the loop. Differential Revision: https://reviews.llvm.org/D33058 llvm-svn: 306884
* Fix ODR violations due to abuse of LLVM_YAML_IS_(FLOW_)?SEQUENCE_VECTORRichard Smith2017-06-304-8/+19
| | | | | | | | | | | | | | | | | | | | | | | | This is a short-term fix for PR33650 aimed to get the modules build bots green again. Remove all the places where we use the LLVM_YAML_IS_(FLOW_)?SEQUENCE_VECTOR macros to try to locally specialize a global template for a global type. That's not how C++ works. Instead, we now centrally define how to format vectors of fundamental types and of string (std::string and StringRef). We use flow formatting for the former cases, since that's the obvious right thing to do; in the latter case, it's less clear what the right choice is, but flow formatting is really bad for some cases (due to very long strings), so we pick block formatting. (Many of the cases that were using flow formatting for strings are improved by this change.) Other than the flow -> block formatting change for some vectors of strings, this should result in no functionality change. Differential Revision: https://reviews.llvm.org/D34907 Corresponding updates to clang, clang-tools-extra, and lld to follow. llvm-svn: 306878
* [Hexagon] Guard the generation of lookup tableSumanth Gundapaneni2017-06-302-0/+67
| | | | | | | | The llvm flag "-hexagon-emit-lookup-tables" guards the generation of lookup table generated from a switch statement. Differential Revision: https://reviews.llvm.org/D34819 llvm-svn: 306877
* [SystemZ] Add all remaining instructionsUlrich Weigand2017-06-309-3/+4172
| | | | | | | | | | | This adds all remaining instructions that were still missing, mostly privileged and semi-privileged system-level instructions. These are provided for use with the assembler and disassembler only. This brings the LLVM assembler / disassembler to parity with the GNU binutils tools. llvm-svn: 306876
* GlobalISel: add G_IMPLICIT_DEF instruction.Tim Northover2017-06-306-22/+52
| | | | | | | | | It looks like there are two target-independent but not GISel instructions that need legalization, IMPLICIT_DEF and PHI. These are already anomalies since their operands have important LLTs attached, so to make things more uniform it seems like a good idea to add generic variants. Starting with G_IMPLICIT_DEF. llvm-svn: 306875
* [Hexagon] Emit jump tables in text section based on a flagSumanth Gundapaneni2017-06-301-0/+57
| | | | | | | | This patch adds a new LLVM flag -hexagon-emit-jt-text which is defaulted to "false". The value "true" emits the switch generated jump tables in text section. Differential Revision: https://reviews.llvm.org/D34820 llvm-svn: 306872
* Revert "[Hexagon] Guard the generation of lookup table"Sumanth Gundapaneni2017-06-301-57/+0
| | | | | | | This reverts commit ae521f4192c3ed0202c047fec993cb59133dd1a0. Wrong commit message llvm-svn: 306871
* [Hexagon] Guard the generation of lookup tableSumanth Gundapaneni2017-06-301-0/+57
| | | | | | | | | The llvm flag "-hexagon-emit-lookup-tables" guards the generation of lookup table from a switch statement. Differential Revision: https://reviews.llvm.org/D34819 llvm-svn: 306869
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