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* [X86][SSE] Regenerate PACKSS tests on 32 + 64-bit targetsSimon Pilgrim2017-10-231-74/+67
| | | | llvm-svn: 316354
* [PassManager] add test to show the new PM uses -latesimplifycfg early; NFCSanjay Patel2017-10-231-0/+95
| | | | llvm-svn: 316351
* AMDGPU: Fix default range in non-kernel functionsMatt Arsenault2017-10-231-0/+22
| | | | | | | | | The range should be assumed to be the hardware maximum if a workitem intrinsic is used in a callable function which does not know the restricted limit of the calling kernel. llvm-svn: 316346
* Update DPPD/DPPS instruction scheduling on btver2.Andrew V. Tischenko2017-10-232-6/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D39046 llvm-svn: 316334
* [X86] Add PTWRITE instruction for assembler and disassembler.Craig Topper2017-10-234-0/+41
| | | | llvm-svn: 316333
* [X86] Add RDPID instruction for assembler and disassembler.Craig Topper2017-10-234-0/+14
| | | | llvm-svn: 316332
* [DAGCombine] Permit combining of shuffles of equivalent splat BUILD_VECTORsSimon Pilgrim2017-10-231-4/+2
| | | | | | | | | | combineShuffleOfScalars is very conservative about shuffled BUILD_VECTORs that can be combined together. This patch adds one additional case - if both BUILD_VECTORs represent splats of the same scalar value but with different UNDEF elements, then we should create a single splat BUILD_VECTOR, sharing only the UNDEF elements defined by the shuffle mask. Differential Revision: https://reviews.llvm.org/D38696 llvm-svn: 316331
* [X86][SSE] Regenerate bitcast-and-setcc testsSimon Pilgrim2017-10-233-93/+93
| | | | | | Avoid the retl/retq changes in an upcoming patch llvm-svn: 316328
* [X86][AVX2] Regenerate AVX2 intrinsics tests on 32 + 64-bit targetsSimon Pilgrim2017-10-233-2122/+1620
| | | | llvm-svn: 316326
* [X86][AVX] Regenerate AVX intrinsics tests on 32 + 64-bit targetsSimon Pilgrim2017-10-233-562/+460
| | | | llvm-svn: 316325
* [X86][F16C] Regenerate F16C schedule testsSimon Pilgrim2017-10-231-28/+28
| | | | llvm-svn: 316324
* Test commit.Artur Gainullin2017-10-231-0/+2
| | | | llvm-svn: 316322
* [llvm-dwarfdump] - Teach tool about few GNU call_sites constants.George Rimar2017-10-231-0/+118
| | | | | | | | | | | | | | This teaches tool about following consants: DW_TAG_GNU_call_site, DW_TAG_GNU_call_site_parameter, DW_AT_GNU_call_site_value, DW_AT_GNU_all_call_sites. Constants documented here: https://sourceware.org/elfutils/DwarfExtensions Differential revision: https://reviews.llvm.org/D39119 llvm-svn: 316321
* [X86] Add test for opportunity to use bzhi X86 instruction instead of ↵Ayman Musa2017-10-231-0/+97
| | | | | | | | load+and instructions. Transformation uploaded for CR in https://reviews.llvm.org/D34141. llvm-svn: 316320
* Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue ↵Andrew V. Tischenko2017-10-231-0/+3
| | | | | | | | was in illegal segment register index. Differential Revision: https://reviews.llvm.org/D38786 llvm-svn: 316319
* [ARM] Allow unrolling of multi-block loops.Sam Parker2017-10-231-0/+316
| | | | | | | | | | | Before, loop unrolling was only enabled for loops with a single block. This restriction has been removed and replaced by: - allow a maximum of two exiting blocks, - a four basic block limit for cores with a branch predictor. Differential Revision: https://reviews.llvm.org/D38952 llvm-svn: 316313
* [X86] Fix disassembly of EVEX rounding control and SAE instructions.Craig Topper2017-10-231-0/+80
| | | | | | Fixes PR31955. llvm-svn: 316308
* Fix invalid ptrtoint in InstCombineYichao Yu2017-10-221-0/+44
| | | | | | | | | | | | | | | | | | | Summary: It's unclear if this is the only thing we can do but at least this is consistent with the check of address space agreement in `isBitCastable`. The code is used at least in both instcombine and jumpthreading though I could only find a way to trigger the invalid cast in instcombine. Reviewers: loladiro, sanjoy, majnemer Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34335 llvm-svn: 316302
* [SimplifyCFG] delay switch condition forwarding to -latesimplifycfgSanjay Patel2017-10-221-1/+1
| | | | | | | | | | | As discussed in D39011: https://reviews.llvm.org/D39011 ...replacing constants with a variable is inverting the transform done by other IR passes, so we definitely don't want to do this early. In fact, it's questionable whether this transform belongs in SimplifyCFG at all. I'll look at moving this to codegen as a follow-up step. llvm-svn: 316298
* Add logic to greedy reg alloc to avoid bad eviction chainsMarina Yatsina2017-10-222-0/+428
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes bugzilla 26810 https://bugs.llvm.org/show_bug.cgi?id=26810 This is intended to prevent sequences like: movl %ebp, 8(%esp) # 4-byte Spill movl %ecx, %ebp movl %ebx, %ecx movl %edi, %ebx movl %edx, %edi cltd idivl %esi movl %edi, %edx movl %ebx, %edi movl %ecx, %ebx movl %ebp, %ecx movl 16(%esp), %ebp # 4 - byte Reload Such sequences are created in 2 scenarios: Scenario #1: vreg0 is evicted from physreg0 by vreg1 Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from) Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.) one of the split intervals ends up evicting vreg2 from physreg1 Evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills Scenario #2 vreg0 is evicted from physreg0 by vreg1 vreg2 is evicted from physreg2 by vreg3 etc Evictee vreg0 is intended for region splitting with split candidate physreg1 Region splitting creates a local interval because of interference with the evictor vreg1 one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from) Another evictee vreg2 is intended for region splitting with split candidate physreg1 one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest). Differential Revision: https://reviews.llvm.org/D35816 Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39 llvm-svn: 316295
* [SimplifyCFG] try harder to forward switch condition to phi (PR34471)Sanjay Patel2017-10-221-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The missed canonicalization/optimization in the motivating test from PR34471 leads to very different codegen: int switcher(int x) { switch(x) { case 17: return 17; case 19: return 19; case 42: return 42; default: break; } return 0; } int comparator(int x) { if (x == 17) return 17; if (x == 19) return 19; if (x == 42) return 42; return 0; } For the first example, we use a bit-test optimization to avoid a series of compare-and-branch: https://godbolt.org/g/BivDsw Differential Revision: https://reviews.llvm.org/D39011 llvm-svn: 316293
* [ARM] Dynamic stack alignment for 16-bit ThumbMomchil Velikov2017-10-223-8/+15
| | | | | | | | | | | This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When targeting processors, which support only the 16-bit Thumb instruction set the compiler ignores the alignment attributes of automatic variables and may silently generate incorrect code. Differential revision: https://reviews.llvm.org/D38143 llvm-svn: 316289
* [X86] Add a pass to convert instruction chains between domains.Guy Blank2017-10-228-666/+2513
| | | | | | | | | | | | | | | | | The pass scans the function to find instruction chains that define registers in the same domain (closures). It then calculates the cost of converting the closure to another domain. If found profitable, the instructions are converted to instructions in the other domain and the register classes are changed accordingly. This commit adds the pass infrastructure and a simple conversion from the GPR domain to the Mask domain. Differential Revision: https://reviews.llvm.org/D37251 Change-Id: Ic2cf1d76598110401168326d411128ae2580a604 llvm-svn: 316288
* [mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld.Nitesh Jain2017-10-222-2/+2
| | | | | | | | | | Reviewers: sdardis Subscribers: jaydeep, bhushan, llvm-commits Differential Revision: https://reviews.llvm.org/D38314 llvm-svn: 316287
* [X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper2017-10-221-0/+11
| | | | | | | | corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. llvm-svn: 316285
* [X86] Don't allow gather/scatter to disassembler if memory operand does not ↵Craig Topper2017-10-221-0/+4
| | | | | | | | use a SIB byte. Fixes PR34998. llvm-svn: 316282
* Reverting r316270 due to failing build bots.Aaron Ballman2017-10-211-16/+16
| | | | | | | http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/12899 http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/7951 llvm-svn: 316276
* [X86][SSE] Add extractps/pextrd equivalence to domain tablesSimon Pilgrim2017-10-2113-91/+81
| | | | | | Differential Revision: https://reviews.llvm.org/D39135 llvm-svn: 316274
* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-211-12/+4
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* [PPC CodeGen] Fix the bitreverse.i64 intrinsic.Fangrui Song2017-10-211-16/+16
| | | | | | | | | | Summary: The two 32-bit words were swapped. Subscribers: nemanjai, kbarton Differential Revision: https://reviews.llvm.org/D38705 llvm-svn: 316270
* [X86][SSE] Add missing extractps scheduling testSimon Pilgrim2017-10-211-0/+62
| | | | llvm-svn: 316262
* [LoopInterchange] Fix phi node ordering miscompile.David Green2017-10-211-0/+90
| | | | | | | | | | | The way that splitInnerLoopHeader splits blocks requires that the induction PHI will be the first PHI in the inner loop header. This makes sure that is actually the case when there are both IV and reduction phis. Differential Revision: https://reviews.llvm.org/D38682 llvm-svn: 316261
* [X86] Do not generate __multi3 for mul i128 on X86Craig Topper2017-10-216-4989/+8381
| | | | | | | | | | | | | | | | Summary: __multi3 is not available on x86 (32-bit). Setting lib call name for MULI_128 to nullptr forces DAGTypeLegalizer::ExpandIntRes_MUL to generate instructions for 128-bit multiply instead of a call to an undefined function. This fixes PR20871 though it may be worth looking at why licm and indvars combine to generate 65-bit multiplies in that test. Patch by Riyaz V Puthiyapurayil Reviewers: craig.topper, schweitz Reviewed By: craig.topper, schweitz Subscribers: RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D38668 llvm-svn: 316254
* [Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek2017-10-201-0/+41
| | | | llvm-svn: 316243
* [WebAssembly] MC: Fix crash when -g specified.Sam Clegg2017-10-201-0/+41
| | | | | | | | | At this point we don't output any debug sections or thier relocations. Differential Revision: https://reviews.llvm.org/D39076 llvm-svn: 316240
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-201-1/+1
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* [Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek2017-10-201-0/+16
| | | | llvm-svn: 316236
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-2015-84/+252
| | | | llvm-svn: 316228
* [X86][SSE] Add missing _mm_extract_ps fast-isel testSimon Pilgrim2017-10-201-1/+16
| | | | llvm-svn: 316226
* [x86] avoid FileCheck assert duplication with retl/retq regex; NFCSanjay Patel2017-10-201-118/+58
| | | | | | | | | | | This was suggested in PR35003: https://bugs.llvm.org/show_bug.cgi?id=35003 32-bit checks may be identical to 64-bit (if we avoid those pesky scalar params!). I'll check in the script change shortly assuming this doesn't anger any bots. llvm-svn: 316223
* Make x86 __ehhandler comdat if parent function isDave Lee2017-10-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change comes from using lld for i686-windows-msvc. Before this change, lld emits an error of: error: relocation against symbol in discarded section: .xdata It's possible that this could be addressed in lld, but I think this change is reasonable on its own. At a high level, this is being generated: A (.text comdat) -> B (.text) -> C (.xdata comdat) Where A is a C++ inline function, which references B, an exception handler thunk, which references C, the exception handling info. With this structure, lld will error when applying relocations to B if the C it references has been discarded (some other C has been selected). This change checks if A is comdat, and if so places the exception registration thunk (B) in the comdata group of A (and B). It appears that MSVC makes the __ehhandler function comdat. Is it possible that duplicate thunks are being emitted into the final binary with other linkers, or are they stripping the unused thunks? Reviewers: rnk, majnemer, compnerd, smeenai Reviewed By: rnk, compnerd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38940 llvm-svn: 316219
* [Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek2017-10-201-0/+63
| | | | | | | | | | | Normally, if the registers holding the induction variable's bounds are redefined inside of the loop's body, the loop cannot be converted to a hardware loop. However, if the redefining instruction is actually loading an immediate value into the register, this conversion is both possible and legal (since the immediate itself will be used in the loop setup in the preheader). llvm-svn: 316218
* [X86] Check all CPU target names. Simon Pilgrim2017-10-201-0/+46
| | | | | | We ignore the 32-bit/64-bit triple but I've tried to use i686 triples for CPUs that don't support x86_64 llvm-svn: 316217
* X86 Tests: Add tests for vector permutes with variable indices. NFC.Zvi Rackover2017-10-203-0/+2584
| | | | | | Basic tests which are the equivalent of single-source shufflevector with variable mask. llvm-svn: 316216
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-10-206-11/+10
| | | | | | | This reverts commit r314507, because the original patch is causing test failures. llvm-svn: 316215
* [ARM] Use post-RA MI scheduler when +use-misched is setEugene Leviant2017-10-201-0/+3
| | | | | | Differential revision: https://reviews.llvm.org/D39100 llvm-svn: 316214
* [X86][AVX512] Regenerate regcall tests.Simon Pilgrim2017-10-202-571/+1860
| | | | | | As part of tracking down machine verifier issues (PR27481) llvm-svn: 316213
* [ValueTracking] Enabling ValueTracking patch by default Nikolai Bozhenov2017-10-201-1/+1
| | | | | | | | | | | | | | | | | (recommit #2 after checking for timeout issue). The original patch was an improvement to IR ValueTracking on non-negative integers. It has been checked in to trunk (D18777, r284022). But was disabled by default due to performance regressions. Perf impact has improved. The patch would be enabled by default. Reviewers: reames, hfinkel Differential Revision: https://reviews.llvm.org/D34101 Patch by: Olga Chupina <olga.chupina@intel.com> llvm-svn: 316208
* Add test case for LoopSink passMax Kazantsev2017-10-201-0/+64
| | | | | | | | | | | This test checks that load from constant memory will be sunk regardless of aliasing stores in the loop. Patch by Daniil Suchkov! Differential Revision: https://reviews.llvm.org/D39113 llvm-svn: 316207
* [AVR] Fix the select-mbb-placement-bug.llDylan McKay2017-10-201-3/+3
| | | | llvm-svn: 316205
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