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* [llvm-cov] Repair a test. NFC.Vedant Kumar2017-09-181-1/+1
| | | | | | | The checks with the MARKER prefix were not being run over the right input, because stderr was not redirected properly. llvm-svn: 313596
* bpf: add inline-asm supportYonghong Song2017-09-181-0/+54
| | | | | | Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 313593
* [ThinLTO/gold] Implement ThinLTO cache pruning supportYi Kong2017-09-181-0/+36
| | | | | | Differential Revision: https://reviews.llvm.org/D37993 llvm-svn: 313592
* Revert r313400 "[DebugInfo] Insert DW_OP_deref when spilling indirect ↵Hans Wennborg2017-09-183-195/+3
| | | | | | | | | | | | | | | | | | | | | | | | | DBG_VALUEs" This caused asserts in Chromium. See http://crbug.com/766261 > Summary: > This comes up in optimized debug info for C++ programs that pass and > return objects indirectly by address. In these programs, > llvm.dbg.declare survives optimization, which causes us to emit indirect > DBG_VALUE instructions. The fast register allocator knows to insert > DW_OP_deref when spilling indirect DBG_VALUE instructions, but the > LiveDebugVariables did not until this change. > > This fixes part of PR34513. I need to look into why this doesn't work at > -O0 and I'll send follow up patches to handle that. > > Reviewers: aprantl, dblaikie, probinson > > Subscribers: qcolombet, hiraditya, llvm-commits > > Differential Revision: https://reviews.llvm.org/D37911 llvm-svn: 313589
* [lit] Update clang and lld to use new config helpers.Zachary Turner2017-09-181-4/+3
| | | | | | | NFC intended here, this only updates clang and lld's lit configs to use some helper functionality in the lit.llvm submodule. llvm-svn: 313579
* [DAGCombiner] fold assertzexts separated by truncSanjay Patel2017-09-188-36/+32
| | | | | | | | | | | | | If we have an AssertZext of a truncated value that has already been AssertZext'ed, we can assert on the wider source op to improve the zext-y knowledge: assert (trunc (assert X, i8) to iN), i1 --> trunc (assert X, i1) to iN This moves a fold from being Mips-specific to general combining, and x86 shows improvements. Differential Revision: https://reviews.llvm.org/D37017 llvm-svn: 313577
* [InstCombine] auto-generate complete checks; NFCSanjay Patel2017-09-181-9/+62
| | | | | | | The code responsible for these transforms has the potential to add 2 instructions and break min/max patterns (PR33301). llvm-svn: 313575
* llvm-dwarfdump: add a --show-parents options when selectively dumping DIEs.Adrian Prantl2017-09-181-0/+15
| | | | llvm-svn: 313567
* Fix typo in testcase.Adrian Prantl2017-09-181-3/+3
| | | | llvm-svn: 313566
* AMDGPU: Start selecting s_xnor_{b32, b64}Konstantin Zhuravlyov2017-09-181-0/+83
| | | | | | Differential Revision: https://reviews.llvm.org/D37981 llvm-svn: 313565
* [DAG, x86] allow store merging before and after legalization (PR34217)Sanjay Patel2017-09-183-77/+34
| | | | | | | | | | | | | | | | | rL310710 allowed store merging to occur after legalization to catch stores that are created late, but this exposes a logic hole seen in PR34217: https://bugs.llvm.org/show_bug.cgi?id=34217 We will miss merging stores if the target lowers vector extracts into target-specific operations. This patch allows store merging to occur both before and after legalization if the target chooses to get maximum merging. I don't think the potential regressions in the other tests are relevant. The tests are for correctness of weird IR constructs rather than perf tests, and I think those are still correct. Differential Revision: https://reviews.llvm.org/D37987 llvm-svn: 313564
* [X86] Make sure we still emit zext for GR32 to GR64 when the source of the ↵Craig Topper2017-09-181-0/+42
| | | | | | | | | | | | zext is AssertZext The AssertZext we might see in this case is only giving information about the lower 32 bits. It isn't providing information about the upper 32 bits. So we should emit a zext. This fixes PR28540. Differential Revision: https://reviews.llvm.org/D37729 llvm-svn: 313563
* [SLP] Add a test for PR34635, NFC.Alexey Bataev2017-09-181-0/+176
| | | | llvm-svn: 313559
* [x86] add tests for PR34217; NFCSanjay Patel2017-09-181-1/+214
| | | | llvm-svn: 313548
* [X86][AVX] Improve (i8 bitcast (v8i1 x)) handling for 256-bit vector compare ↵Simon Pilgrim2017-09-181-21/+9
| | | | | | | | results. As commented on D37849, AVX1 targets were missing a chance to use vmovmskps for v8f32/v8i32 results for bool vector bitcasts llvm-svn: 313547
* [x86] regenerate checks; NFCSanjay Patel2017-09-181-16/+17
| | | | llvm-svn: 313545
* [LoopVectorizer] Add more testcases for PR33804.Manoj Gupta2017-09-182-0/+96
| | | | | | | | | | | | | | | | Summary: Add test cases when float <-> pointer types conversion is triggered in presence of load instructions. Reviewers: Ayal, srhines, mkuper, rengolin Reviewed By: rengolin Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D37967 llvm-svn: 313544
* [SelectionDAG] Add BITCAST handling to ComputeNumSignBits for splatted sign ↵Simon Pilgrim2017-09-186-1041/+701
| | | | | | | | | | | | bits. For cases where we are BITCASTing to vectors of smaller elements, then if the entire source was a splatted sign (src's NumSignBits == SrcBitWidth) we can say that the dst's NumSignBit == DstBitWidth, as we're just splitting those sign bits across multiple elements. We could generalize this but at the moment the only use case I have is to peek through bitcasts to vector comparison results. Differential Revision: https://reviews.llvm.org/D37849 llvm-svn: 313543
* [X86] Fix two more places to prefer VPERMQ/PD over VPERM2X128 when AVX2 is ↵Craig Topper2017-09-1815-449/+407
| | | | | | | | | | | | enabled The shuffle combining and lowerVectorShuffleAsLanePermuteAndBlend were both still trying to use VPERM2XF128 for unary shuffles when AVX2 is enabled. VPERM2X128 takes two inputs meaning when we use it for a unary shuffle one of those inputs is left undefined creating a false dependency on whatever register gets allocated there. If we have VPERMQ/PD we should prefer those since they only have a single input. Differential Revision: https://reviews.llvm.org/D37947 llvm-svn: 313542
* [AArch64] Add V8_2aOps feature to Cortex-A55 and 75Sam Parker2017-09-183-0/+11
| | | | | | | | | | Add the missing hardware features the ProcA55 and ProcA75 feature. These are already enabled via the target parser, but I had missed them in the backend. Differential Revision: https://reviews.llvm.org/D37974 llvm-svn: 313535
* [ARM] Implement isTruncateFreeSam Parker2017-09-181-0/+25
| | | | | | | | | | Implement the isTruncateFree hooks, lifted from AArch64, that are used by TargetTransformInfo. This allows simplifycfg to reduce the test case into a single basic block. Differential Revision: https://reviews.llvm.org/D37516 llvm-svn: 313533
* [X86][SSE] Improve support for vselect(Cond, 0, X) -> ANDN(Cond, X)Simon Pilgrim2017-09-182-23/+11
| | | | | | | | As discussed on PR28925 and D37849. Differential Revision: https://reviews.llvm.org/D37975 llvm-svn: 313532
* [ARM] Fix for indexed dot product instruction descriptionsSjoerd Meijer2017-09-181-0/+22
| | | | | | | | | | | The indexed dot product instructions only accept the lower 16 D-registers as the indexed register, but we were e.g. incorrectly accepting: vudot.u8 d16,d16,d18[0] Differential Revision: https://reviews.llvm.org/D37968 llvm-svn: 313531
* [dwarfdump] Make .eh_frame an alias for .debug_frameJonas Devlieghere2017-09-184-8/+7
| | | | | | | | | | | | | | | | | | | | This patch makes the `.eh_frame` extension an alias for `.debug_frame`. Up till now it was only possible to dump the section using objdump, but not with dwarfdump. Since the two are essentially interchangeable, we dump whichever of the two is present. As a workaround, this patch also adds parsing for 3 currently unimplemented CFA instructions: `DW_CFA_def_cfa_expression`, `DW_CFA_expression`, and `DW_CFA_val_expression`. Because I lack the required knowledge, I just parse the fields without actually creating the instructions. Finally, this also fixes the typo in the `.debug_frame` section name which incorrectly contained a trailing `s`. Differential revision: https://reviews.llvm.org/D37852 llvm-svn: 313530
* [X86][SSE] Add vselect with zero tests (PR28925)Simon Pilgrim2017-09-181-0/+67
| | | | llvm-svn: 313529
* [X86FixupBWInsts] More precise register liveness if no <imp-use> on MOVs.Nikolai Bozhenov2017-09-1815-234/+386
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Subregister liveness tracking is not implemented for X86 backend, so sometimes the whole super register is said to be live, when only a subregister is really live. That might happen if the def and the use are located in different MBBs, see added fixup-bw-isnt.mir test. However, using knowledge of the specific instructions handled by the bw-fixup-pass we can get more precise liveness information which this change does. Reviewers: MatzeB, DavidKreitzer, ab, andrew.w.kaylor, craig.topper Reviewed By: craig.topper Subscribers: n.bozhenov, myatsina, llvm-commits, hiraditya Patch by Andrei Elovikov <andrei.elovikov@intel.com> Differential Revision: https://reviews.llvm.org/D37559 llvm-svn: 313524
* [X86][Codegen] adding masked gathers tests for avx2Mohammed Agabaria2017-09-181-0/+915
| | | | | | | | | related to patch: https://reviews.llvm.org/D35772 adding llvm gathers test before gathers codegen support. Differential Revision: https://reviews.llvm.org/D37800 llvm-svn: 313516
* [XRay][tools] Support tail-call exits before we write them in the runtimeDean Michael Berris2017-09-181-1/+1
| | | | | | | | | | | | | | | | | Summary: This change adds support for explicit tail-exit records to be written by the XRay runtime. This lets us differentiate the tail exit records/events in the log, and allows us to treat those exit events especially in the future. For now we allow printing those out in YAML (and reading them in). Reviewers: kpw, pelikan Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37964 llvm-svn: 313514
* [X86] Teach the execution domain fixing tables to use movlhps inplace of ↵Craig Topper2017-09-1841-360/+360
| | | | | | | | unpcklpd for the packed single domain. MOVLHPS has a smaller encoding than UNPCKLPD in the legacy encodings. With VEX and EVEX encodings it doesn't matter. llvm-svn: 313509
* [X86] Teach execution domain fixing to convert between FP and int unpack ↵Craig Topper2017-09-1842-743/+573
| | | | | | instructions. llvm-svn: 313508
* [X86] Teach execution domain fixing to convert between VPERMILPS and VPSHUFD.Craig Topper2017-09-1840-486/+381
| | | | llvm-svn: 313507
* [X86] Teach shuffle lowering to use MOVLHPS/MOVHLPS for lowering v4f32 unary ↵Craig Topper2017-09-171-2/+2
| | | | | | shuffles with SSE1 only. llvm-svn: 313504
* [X86] Add a couple more unary shuffles to the sse1 shuffle test.Craig Topper2017-09-171-0/+18
| | | | | | These can be implemented with movlhps and movhlps. llvm-svn: 313503
* Adding test cases for PR34629 & PR34634.Jatin Bhateja2017-09-172-0/+119
| | | | | | Differential Revision: https://reviews.llvm.org/D37962 llvm-svn: 313490
* [RISCV] Add support for disassemblyAlex Bradbury2017-09-171-0/+4
| | | | | | | | | This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s has been updated appropriately. Differential Revision: https://reviews.llvm.org/D23567 llvm-svn: 313486
* [RISCV] Add support for all RV32I instructionsAlex Bradbury2017-09-172-3/+197
| | | | | | | | | | This patch supports all RV32I instructions as described in the RISC-V manual. A future patch will add support for pseudoinstructions and other instruction expansions (e.g. 0-arg fence -> fence iorw, iorw). Differential Revision: https://reviews.llvm.org/D23566 llvm-svn: 313485
* [GlobalISel][X86] Legalize i1 G_ADD/G_SUB/G_MUL/G_XOR/G_OR/G_AND instructions.Igor Breger2017-09-1711-15/+293
| | | | llvm-svn: 313483
* [GlobalISel][X86] Use correct physical register in mir tests.NFC.Igor Breger2017-09-1719-124/+122
| | | | llvm-svn: 313479
* [GlobalISel][X86] G_FCONSTANT support.Igor Breger2017-09-174-7/+173
| | | | | | | | | | | | | | Summary: G_FCONSTANT support, port the implementation from X86FastIsel. Reviewers: zvi, delena, guyblank Reviewed By: delena Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D37734 llvm-svn: 313478
* [llvm-symbolizer] Fix coff-dwarf.testZachary Turner2017-09-161-1/+1
| | | | | | | | | | | | | | | | | | This was a bug in the test that was only exposed as a result of refactoring some code in lit configuration files. Previously, llvm's lit configuration would only set the target-windows feature if the system was also windows. Since cross-compilation is a thing, this isn't correct. target-windows should be set independently of system-windows. Adding to that bug, this particular test then checked for target-windows when it really meant "can I call a certain API on the host machine", which is what system-windows is for. Ultimately, this test only works if *both* the target and host are Windows, so I've updated the test to reflect that. llvm-svn: 313468
* Resubmit "Add a shared llvm.lit module that all test suites can use."Zachary Turner2017-09-162-157/+18
| | | | | | | | There were some issues surrounding Py2 / Py3 compatibility, but I've now tested with both Py2 and Py3 and everything seems to work. llvm-svn: 313467
* llvm-dwarfdump: support a --show-children optionAdrian Prantl2017-09-162-1/+22
| | | | | | | This will print all children of a DIE when selectively printing only one DIE at a given offset. llvm-svn: 313464
* llvm-dwarfdump: Add support for -debug-types=<offset>.Adrian Prantl2017-09-161-0/+8
| | | | llvm-svn: 313463
* [llvm-readobj] - Teach tool to report error if some section is in multiple ↵George Rimar2017-09-161-0/+77
| | | | | | | | | | | | COMDAT groups at once. readelf tool reports an error when output contains the same section in multiple COMDAT groups. That can be useful. Path teaches llvm-readobj to do the same. Differential revision: https://reviews.llvm.org/D37567 llvm-svn: 313459
* [x86] enable storeOfVectorConstantIsCheap() target hookSanjay Patel2017-09-162-65/+59
| | | | | | | | | | | | | | This allows vector-sized store merging of constants in DAGCombiner using the existing code in MergeConsecutiveStores(). All of the twisted logic that decides exactly what vector operations are legal and fast for each particular CPU are handled separately in there using the appropriate hooks. For the motivating tests in merge-store-constants.ll, we already produce the same vector code in IR via the SLP vectorizer. So this is just providing a backend backstop for code that doesn't go through that pass (-O1). More details in PR24449: https://bugs.llvm.org/show_bug.cgi?id=24449 (this change should be the last step to resolve that bug) Differential Revision: https://reviews.llvm.org/D37451 llvm-svn: 313458
* [X86] Add isel patterns to be able to fold loads into VPERM2F128 even when ↵Craig Topper2017-09-161-2/+2
| | | | | | | | | | the load is on the first input to the SDNode. We just need to toggle bits 1 and 5 of the immediate and swap the sources. The peephole pass could trigger commuting/folding for this later, but its easy enough to fix in isel. Disable the peephole pass on the main vperm2x128 test so we know we're doing this through isel. llvm-svn: 313455
* [X86] Remove unused check lines that got left behind when I moved tests to ↵Craig Topper2017-09-161-15/+0
| | | | | | the instrinsic upgrade file and regenerated. llvm-svn: 313454
* [X86] Remove the vperm2f128 test file I just added in r313450.Craig Topper2017-09-161-229/+0
| | | | | | I missed the we already had a pretty thorough test file for these instructions. llvm-svn: 313451
* [X86] Remove VPERM2F128/VPERM2I128 intrinsics and autoupgrade to native ↵Craig Topper2017-09-166-377/+323
| | | | | | | | shuffles. I've moved the test cases from the InstCombine optimizations to the backend to keep the coverage we had there. It covered every possible immediate so I've preserved the resulting shuffle mask for each of those immediates. llvm-svn: 313450
* [X86] Fix some FileCheck lines that use the wrong prefix.Craig Topper2017-09-161-12/+12
| | | | | | Assume they were moved during autoupgrading and not changed. llvm-svn: 313448
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