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* [PPC] Use alias symbols in address computation.Rafael Espindola2014-05-261-0/+31
| | | | | | | This seems to match what gcc does for ppc and what every other llvm backend does. llvm-svn: 209638
* AArch64: force i1 to be zero-extended at an ABI boundary.Tim Northover2014-05-261-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is debatable. There are two possible approaches, neither of which is really satisfactory: 1. Use "@foo(i1 zeroext)" to mean an extension to 32-bits on Darwin, and 8 bits otherwise. 2. Redefine "@foo(i1)" to mean that the i1 is extended by the caller to 8 bits. This goes against the spirit of "zeroext" I think, but it's a bit of a vague construct anyway (by definition you're going to extend to the amount required by the ABI, that's why it's the ABI!). This implements option 2. The DAG machinery really isn't setup for the first (there's a fairly strong assumption that "zeroext" goes to at least the smallest register size), and even if it was the resulting DAG looks like it would be inferior in many cases. Theoretically we could add AssertZext nodes in the consumers of ABI-passed values too now, but this actually seems to make the code worse in practice by making truncation proceed in two steps. The code produced is equally valid if we continue to assume only the low bit is defined. Should fix PR19850 llvm-svn: 209637
* AArch64: simplify calling conventions slightly.Tim Northover2014-05-261-0/+8
| | | | | | | | | We can eliminate the custom C++ code in favour of some TableGen to check the same things. Functionality should be identical, except for a buffer overrun that was present in the C++ code and meant webkit failed if any small argument needed to be passed on the stack. llvm-svn: 209636
* [AArch64] Add store + add folding regression tests for the load/store ↵Tilmann Scheller2014-05-261-2/+66
| | | | | | | | | | | | | | | | optimization pass. Add tests for the following transform: str X, [x0, #32] ... add x0, x0, #32 -> str X, [x0, #32]! with X being either w1, x1, s0, d0 or q0. llvm-svn: 209627
* [AArch64] Add more regression tests for the load/store optimization pass.Tilmann Scheller2014-05-261-11/+81
| | | | | | | | | | | | | | Cover the following cases: ldr X, [x0, #32] ... add x0, x0, #32 -> ldr X, [x0, #32]! with X being either w1, x1, s0, d0 or q0. llvm-svn: 209624
* Remove accidentally committed whitespace.Tilmann Scheller2014-05-261-2/+2
| | | | llvm-svn: 209619
* [AArch64] Add a regression test for the load store optimizer.Tilmann Scheller2014-05-261-0/+31
| | | | | | | | We have a couple of regression tests for load/store pairing, but (to my knowledge) there are no regression tests for the load/store + add/sub folding. As a first step towards increased test coverage of this area, this commit adds a test for one instance of a load + add to pre-indexed load transformation. llvm-svn: 209618
* DebugInfo: Test linkonce-odr functions under LTO.David Blaikie2014-05-261-0/+74
| | | | | | | | | | | | | | | | | | | | | | | This was previously regressed/broken by r192749 (reverted due to this issue in r192938) and I was about to break it again by accident with some more invasive changes that deal with the subprogram lists. So to avoid that and further issues - here's a test. It's a pretty basic test - in both r192749 and my impending case, this test would crash, but checking the basics (that we put a subprogram in just one of the two CUs) seems like a good start. We still get this wrong in weird ways if the linkonce-odr function happens to not be identical in the metadata (because it's defined in two different files (hence the # line directives in this test), etc) even though it meets the language requirements (identical token stream) for such a thing. That results in two subprogram DIEs, but only one of them gets the parameter and high/low pc information, etc. We probably need to use the DIRef infrastructure to deduplicate functions as we do types to address this issue - or perhaps teach the BC linker to remove the duplicate entries in subprogram lists? llvm-svn: 209614
* Just check the entire string.Rafael Espindola2014-05-262-64/+64
| | | | | | Thanks to David Blaikie for the suggestion. llvm-svn: 209610
* DebugInfo: Fix inlining with #file directives a little harderDavid Blaikie2014-05-251-0/+3
| | | | | | | | | | | Seems my previous fix was insufficient - we were still not adding the inlined function to the abstract scope list. Which meant it wasn't flagged as inline, didn't have nested lexical scopes in the abstract definition, and didn't have abstract variables - so the inlined variable didn't reference an abstract variable, instead being described completely inline. llvm-svn: 209602
* Streamline test case by avoiding a temporary file and piping llc output ↵David Blaikie2014-05-251-2/+1
| | | | | | | | | straight to llvm-dwarfdump We still do temporary files in many cases, just updating this particular one because I was debugging it and made this change while doing so. llvm-svn: 209601
* Emit data or code export directives based on the type.Rafael Espindola2014-05-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | Currently we look at the Aliasee to decide what type of export directive to use. It seems better to use the type of the alias directly. This is similar to how we handle the alias having the same address but other attributes (linkage, visibility) from the aliasee. With this patch it is now possible to do things like target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc" @foo = global [6 x i8] c"\B8*\00\00\00\C3", section ".text", align 16 @f = dllexport alias i32 (), [6 x i8]* @foo !llvm.module.flags = !{!0} !0 = metadata !{i32 6, metadata !"Linker Options", metadata !1} !1 = metadata !{metadata !2, metadata !3} !2 = metadata !{metadata !"/DEFAULTLIB:libcmt.lib"} !3 = metadata !{metadata !"/DEFAULTLIB:oldnames.lib"} llvm-svn: 209600
* Make these CHECKs a bit more strict.Rafael Espindola2014-05-252-62/+62
| | | | | | The " at the end of the line makes sure we matched the entire directive. llvm-svn: 209599
* CodeGen: Make MachineBasicBlock::back skip to the beginning of the last bundle.Benjamin Kramer2014-05-242-0/+78
| | | | | | | | | | | | This makes front/back symmetric with begin/end, avoiding some confusion. Added instr_front/instr_back for the old behavior, corresponding to instr_begin/instr_end. Audited all three in-tree users of back(), all of them look like they don't want to look inside bundles. Fixes an assertion (PR19815) when generating debug info on mips, where a delay slot was bundled at the end of a branch. llvm-svn: 209580
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-24519-5211/+4988
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-24268-27975/+6
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* llvm/test/Object/ar-error.test: Don't check the message "No such file or ↵NAKAMURA Takumi2014-05-241-1/+2
| | | | | | | | directory". It didn't match on non-English version of Windows. llvm-svn: 209570
* Implement sext(C1 + C2*X) --> sext(C1) + sext(C2*X) andMichael Zolotukhin2014-05-241-0/+175
| | | | | | | | | | | sext{C1,+,C2} --> sext(C1) + sext{0,+,C2} transformation in Scalar Evolution. That helps SLP-vectorizer to recognize consecutive loads/stores. <rdar://problem/14860614> llvm-svn: 209568
* ARM64: extract a 32-bit subreg when selecting an inreg extendTim Northover2014-05-241-2/+135
| | | | | | | | After the load/store refactoring, we were sometimes trying to feed a GPR64 into a 32-bit register offset operand. This failed in copyPhysReg. llvm-svn: 209566
* DebugInfo: Generalize some tests to handle variations in attribute ordering.David Blaikie2014-05-2312-58/+73
| | | | | | | | | | | | | | | | In an effort to fix inlined debug info in situations where the out of line definition of a function preceeds any inlined usage, the order in which some attributes are added to subprogram DIEs may change. (in essence, definition-necessary attributes like DW_AT_low_pc/high_pc will be added immediately, but the names, types, and other features will be delayed to module end where they may either be added to the subprogram DIE or instead reference an abstract definition for those values) These tests can be generalized to be resilient to this change. 5 or so tests actually have to be incompatibly changed to cope with this reordering and will go along with the change that affects the order. llvm-svn: 209554
* DebugInfo: Generalize a test case to not depend on abbreviation numbering.David Blaikie2014-05-231-8/+8
| | | | | | | It's an unnecessary detail for this test and just gets in the way when making unrelated changes to the output in this test. llvm-svn: 209553
* Test case comments. Fix sloppiness.Andrew Trick2014-05-231-2/+2
| | | | llvm-svn: 209551
* DebugInfo: Put concrete definitions referencing abstract definitions in the ↵David Blaikie2014-05-231-0/+92
| | | | | | | | | | | | | | | | | | | same scope as the abstract definition. This seems like a simple cleanup/improved consistency, but also helps lay the foundation to fix the bug mentioned in the test case: concrete definitions preceeding any inlined usage aren't properly split into concrete + abstract (because they're not known to need it until it's too late). Once we start deferring this choice until later, we won't have the choice to put concrete definitions for inlined subroutines in a different scope from concrete definitions for non-inlined subroutines (since we won't know at time-of-construction which one it'll be). This change brings those two cases into alignment ahead of that future chaneg/fix. llvm-svn: 209547
* Fix and improve SCEV ComputeBackedgeTankCount.Andrew Trick2014-05-231-0/+56
| | | | | | | | | | | | | This is a follow-up to r209358: PR19799: Indvars miscompile due to an incorrect max backedge taken count from SCEV. That fix was incomplete as pointed out by Arnold and Michael Z. The code was also too confusing. It needed a careful rewrite with more unit tests. This version will also happen to optimize more cases. <rdar://17005101> PR19799: Indvars miscompile... llvm-svn: 209545
* Revert part of "Fix broken FileCheck prefixes"Nico Rieck2014-05-232-11/+11
| | | | | | This reverts part of commit r209538. llvm-svn: 209544
* Use alias linkage and visibility to decide tls access mode.Rafael Espindola2014-05-232-3/+3
| | | | | | | | | | | | | | | | | This matches both what we do for the non-thread case and what gcc does. With this patch clang would match gcc's behaviour in static __thread int a = 42; extern __thread int b __attribute__((alias("a"))); int *f(void) { return &a; } int *g(void) { return &b; } if not for pr19843. Manually writing the IL does produce the same access modes. It is also a step in the direction of fixing pr19844. llvm-svn: 209543
* Remove unused CHECK linesNico Rieck2014-05-231-4/+0
| | | | llvm-svn: 209539
* Fix broken FileCheck prefixesNico Rieck2014-05-235-14/+14
| | | | llvm-svn: 209538
* Add the extracted constant offset using GEPJingyue Wu2014-05-232-13/+30
| | | | | | | | | | | | | Fixed a TODO in r207783. Add the extracted constant offset using GEP instead of ugly ptrtoint+add+inttoptr. Using GEP simplifies future optimizations and makes IR easier to understand. Updated all affected tests, and added a new test in split-gep.ll to cover a corner case where emitting uglygep is necessary. llvm-svn: 209537
* Convert test to use FileCheck.Rafael Espindola2014-05-231-1/+5
| | | | llvm-svn: 209528
* [mips] Work around inconsistency in llvm-mc's placement of fixup markersDaniel Sanders2014-05-234-11/+20
| | | | | | | | | | | | | | | | | | | Summary: Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly position llvm-mc's fixup placeholders for big-endian. See PR19836 for full details of the issue. To summarize, the fixup placeholders do not account for endianness properly and the implementations of getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset from different ends of the instruction encoding to compensate. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3889 llvm-svn: 209514
* [mips][mips64r6] t(eq|ge|lt|ne)i and t(ge|lt)iu are not available in ↵Daniel Sanders2014-05-233-0/+34
| | | | | | | | | | | | | | MIPS32r6/MIPS64r6 Summary: Depends on D3872 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3891 llvm-svn: 209513
* [mips][mips64r6] [ls][dw][lr] are not available in MIPS32r6/MIPS64r6Daniel Sanders2014-05-237-102/+535
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Instead the system is required to provide some means of handling unaligned load/store without special instructions. Options include full hardware support, full trap-and-emulate, and hybrids such as hardware support within a cache line and trap-and-emulate for multi-line accesses. MipsSETargetLowering::allowsUnalignedMemoryAccesses() has been configured to assume that unaligned accesses are 'fast' on the basis that I expect few hardware implementations will opt for pure-software handling of unaligned accesses. The ones that do handle it purely in software can override this. mips64-load-store-left-right.ll has been merged into load-store-left-right.ll The stricter testing revealed a Bits!=Bytes bug in passByValArg(). This has been fixed and the variables renamed to clarify the units they hold. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3872 llvm-svn: 209512
* [asan] properly instrument memory accesses that have small alignment ↵Kostya Serebryany2014-05-233-9/+25
| | | | | | (smaller than min(8,size)) by making two checks instead of one. This may slowdown some cases, e.g. long long on 32-bit or wide loads produced after loop unrolling. The benefit is higher sencitivity. llvm-svn: 209508
* [YAML] Add an optional argument `EnumMask` to the `yaml::IO::bitSetCase()`.Simon Atanasyan2014-05-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some bit-set fields used in ELF file headers in fact contain two parts. The first one is a regular bit-field. The second one is an enumeraion. For example ELF header `e_flags` for MIPS target might contain the following values: Bit-set values: EF_MIPS_NOREORDER = 0x00000001 EF_MIPS_PIC = 0x00000002 EF_MIPS_CPIC = 0x00000004 EF_MIPS_ABI2 = 0x00000020 Enumeration: EF_MIPS_ARCH_32 = 0x50000000 EF_MIPS_ARCH_64 = 0x60000000 EF_MIPS_ARCH_32R2 = 0x70000000 EF_MIPS_ARCH_64R2 = 0x80000000 For printing bit-sets we use the `yaml::IO::bitSetCase()`. It does not support bit-set/enumeration combinations and prints too many flags from an enumeration part. This patch fixes this problem. New method `yaml::IO::maskedBitSetCase()` handle "enumeration" part of bitset defined by provided mask. Patch reviewed by Nick Kledzik and Sean Silva. llvm-svn: 209504
* llvm-ar: Output the file we errored on.Filipe Cabecinhas2014-05-231-0/+5
| | | | llvm-svn: 209500
* DebugInfo: Fix cross-CU references for scopes (and variables within those ↵David Blaikie2014-05-231-0/+6
| | | | | | | | scopes) in abstract definitions of cross-CU inlined functions Found by Adrian Prantl during post-commit review of r209335. llvm-svn: 209498
* MC: remove unnecessary restriction on testsSaleem Abdulrasool2014-05-237-7/+0
| | | | | | | | | | Rafael correctly pointed out that the restriction is unnecessary. Although the tests are intended to ensure that we dont abort due to an assertion, running the tests in all modes is better since it also ensures that we dont crash without assertions. Always run these tests to ensure that we can handle invalid input correctly. llvm-svn: 209496
* [ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD ↵Jiangning Liu2014-05-231-0/+172
| | | | | | with swapped input vectors. llvm-svn: 209495
* ScalarEvolution: Fix handling of AddRecs in isKnownPredicateJustin Bogner2014-05-231-0/+30
| | | | | | | | | | | | | ScalarEvolution::isKnownPredicate() can wrongly reduce a comparison when both the LHS and RHS are SCEVAddRecExprs. This checks that both LHS and RHS are guarded in the case when both are SCEVAddRecExprs. The test case is against indvars because I could not find a way to directly test SCEV. Patch by Sanjay Patel! llvm-svn: 209487
* R600: Try to convert BFE back to standard bit ops when possible.Matt Arsenault2014-05-224-11/+276
| | | | | | | This allows existing DAG combines to work on them, and then we can re-match to BFE if necessary during instruction selection. llvm-svn: 209462
* R600: Add dag combine for BFEMatt Arsenault2014-05-223-0/+751
| | | | llvm-svn: 209461
* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-221-0/+15
| | | | llvm-svn: 209460
* R600: Expand mul24 for GPUs without itMatt Arsenault2014-05-222-3/+10
| | | | llvm-svn: 209458
* R600: Expand mad24 for GPUs without itMatt Arsenault2014-05-222-0/+14
| | | | llvm-svn: 209457
* R600: Add intrinsics for mad24Matt Arsenault2014-05-222-0/+26
| | | | llvm-svn: 209456
* [X86] Improve the lowering of BITCAST from MVT::f64 to MVT::v4i16/MVT::v8i8.Andrea Di Biagio2014-05-223-82/+157
| | | | | | | | | | | | | This patch teaches the x86 backend how to efficiently lower ISD::BITCAST dag nodes from MVT::f64 to MVT::v4i16 (and vice versa), and from MVT::f64 to MVT::v8i8 (and vice versa). This patch extends the logic from revision 208107 to also handle MVT::v4i16 and MVT::v8i8. Also, this patch correctly propagates Undef values when performing the widening of a vector (example: when widening from v2i32 to v4i32, the upper 64bits of the resulting vector are 'undef'). llvm-svn: 209451
* Add support for missed and analysis optimization remarks.Diego Novillo2014-05-221-0/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds two new diagnostics: -pass-remarks-missed and -pass-remarks-analysis. They take the same values as -pass-remarks but are intended to be triggered in different contexts. -pass-remarks-missed is used by LLVMContext::emitOptimizationRemarkMissed, which passes call when they tried to apply a transformation but couldn't. -pass-remarks-analysis is used by LLVMContext::emitOptimizationRemarkAnalysis, which passes call when they want to inform the user about analysis results. The patch also: 1- Adds support in the inliner for the two new remarks and a test case. 2- Moves emitOptimizationRemark* functions to the llvm namespace. 3- Adds an LLVMContext argument instead of making them member functions of LLVMContext. Reviewers: qcolombet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3682 llvm-svn: 209442
* Segmented stacks: omit __morestack call when there's no frame.Tim Northover2014-05-223-11/+62
| | | | | | Patch by Florian Zeitz llvm-svn: 209436
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-223-129/+78
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
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