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* On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume.John McCall2011-05-291-0/+29
| | | | | | | This is important for the correct lowering of unwind instructions (which doesn't matter at all) and llvm.eh.resume calls (which does). llvm-svn: 132291
* Obey the isVolatile bit on memory intrinsics when analyzing uses of a globalNick Lewycky2011-05-291-0/+19
| | | | | | | | | variable. Noticed by inspection. Simulate memset in EvaluateFunction where the target of the memset and the value we're setting are both the null value. Fixes PR10047! llvm-svn: 132288
* Use %rbp on a 64 bit test.Rafael Espindola2011-05-291-1/+1
| | | | llvm-svn: 132279
* Move ARM specific test into the ARM subdir.Benjamin Kramer2011-05-281-0/+0
| | | | llvm-svn: 132255
* ConstantFoldInstOperands doesn't like compares, hand it off to instsimplify ↵Benjamin Kramer2011-05-281-0/+10
| | | | | | | | instead. Fixes PR10040. llvm-svn: 132254
* Implement and document the llvm.eh.resume intrinsic, which isJohn McCall2011-05-281-13/+18
| | | | | | | | | | | | | | | | | transformed by the inliner into a branch to the enclosing landing pad (when inlined through an invoke). If not so optimized, it is lowered DWARF EH preparation into a call to _Unwind_Resume (or _Unwind_SjLj_Resume as appropriate). Its chief advantage is that it takes both the exception value and the selector value as arguments, meaning that there is zero effort in recovering these; however, the frontend is required to pass these down, which is not actually particularly difficult. Also document the behavior of landing pads a bit better, and make it clearer that it's okay that personality functions don't always land at landing pads. This is just a fact of life. Don't write optimizations that rely on pushing things over an unwind edge. llvm-svn: 132253
* Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairsBruno Cardoso Lopes2011-05-281-0/+33
| | | | | | | | to load/store i64 values. Since there's no current support to explicitly declare such restrictions, implement it by using specific hardcoded register pairs during isel. llvm-svn: 132248
* Implement the 'M' output modifier for arm inline asm. This is fairlyEric Christopher2011-05-281-10/+27
| | | | | | | | | register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
* Add missing newlines.Chad Rosier2011-05-284-4/+4
| | | | llvm-svn: 132241
* Define a wrapper node for target constant nodes (tglobaladdr, etc.).Akira Hatanaka2011-05-281-1/+17
| | | | | | Need this to prevent emitting illegal conditional move instructions. llvm-svn: 132240
* Fix test cases that were previously using grep to use FileCheckChad Rosier2011-05-2812-37/+56
| | | | llvm-svn: 132237
* Fix the remaining atomic intrinsics to use the right register classes on Thumb2,Cameron Zwarich2011-05-271-0/+103
| | | | | | and add some basic tests for them. llvm-svn: 132235
* ARM asm parser wasn't able to parse a "mov" instruction while in ThumbBruno Cardoso Lopes2011-05-271-0/+3
| | | | | | | mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode, default to the Thumb 1 versions/encodings. llvm-svn: 132233
* Force a triple to make this test pass on Darwin.Eli Friedman2011-05-271-2/+2
| | | | llvm-svn: 132228
* Add a GR32_NOREX_NOSP register class and fix a bug where ↵Cameron Zwarich2011-05-271-0/+41
| | | | | | | | | getMatchingSuperRegClass() was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032. llvm-svn: 132225
* Fix a regression I recently introduced by removing DwarfRegNum ofRafael Espindola2011-05-271-0/+27
| | | | | | | | | | subregisters: When a value is in a subregister, at least report the location as being the superregister. We should extend the .td files to encode the bit range so that we can produce a DW_OP_bit_piece. llvm-svn: 132224
* Make size computation less brittle.Rafael Espindola2011-05-275-5/+21
| | | | llvm-svn: 132222
* Add the suffix to the Win64 EH data sections' names if given. Add a test forCharles Davis2011-05-271-0/+37
| | | | | | this. XFAIL'd, because the COFF AsmParser can't handle .section yet. llvm-svn: 132220
* Typo is test caseChad Rosier2011-05-271-2/+2
| | | | llvm-svn: 132214
* Make room for register allocation to improve.Jakob Stoklund Olesen2011-05-271-1/+1
| | | | llvm-svn: 132213
* Don't use movw / movt for iOS static codegen for now to workaround some ↵Evan Cheng2011-05-271-4/+4
| | | | | | tools issues. rdar://9514789 llvm-svn: 132211
* Delete a test that is no longer relevant.Jakob Stoklund Olesen2011-05-271-52/+0
| | | | | | | | | | | | | | | | | | | According to PR2536, the old spiller had trouble with the IMPLICIT_DEF in this code: %reg1028<def> = MOV16rm %reg0, 1, %reg0, <ga:g_5>, Mem:LD(2,2) [g_5 + 0] %reg1039<def> = IMPLICIT_DEF %reg1038<def> = INSERT_SUBREG %reg1039, %reg1028, 2 %reg1025<def> = AND32ri %reg1038, 65534, %%EFLAGS<imp-def> However, today we emit a zero-extending load instead: %vreg10<def> = MOVZX32rm16 %noreg, 1, %noreg, <ga:@g_5>, %noreg; %mem:LD2[@g_5] GR32:%vreg10 %vreg0<def> = AND32ri %vreg10, 65534, %%EFLAGS<imp-def,dead>; %GR32:%vreg0,%vreg10 This makes the test pointless since it no longer creates the spiller hazard. llvm-svn: 132210
* CRC32 intrinsics were renamed at revision 132163. This submissionChad Rosier2011-05-272-0/+16
| | | | | | | | fixes aliasing issues with the old and new names as well as adds test cases for the auto-upgrader. Fixes rdar 9472944. llvm-svn: 132207
* Add iOS testEvan Cheng2011-05-271-10/+29
| | | | llvm-svn: 132203
* Fix the inliner to maintain the current de facto invoke semantics:John McCall2011-05-271-0/+103
| | | | | | | | | | | | | | - the selector for the landing pad must provide all available information about the handlers, filters, and cleanups within that landing pad - calls to _Unwind_Resume must be converted to branches to the enclosing lpad so as to avoid re-entering the unwinder when the lpad claimed it was going to handle the exception in some way This is quite specific to libUnwind-based unwinding. In an effort to not interfere too badly with other unwinders, and with existing hacks in frontends, this only triggers on _Unwind_Resume (not _Unwind_Resume_or_Rethrow) and does nothing with selectors if it cannot find a selector call for either lpad. llvm-svn: 132200
* And fix the test in r132194.Eli Friedman2011-05-271-1/+1
| | | | llvm-svn: 132196
* Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076Eli Friedman2011-05-271-0/+9
| | | | llvm-svn: 132194
* Select DW_AT_const_value size based on variable size.Devang Patel2011-05-271-0/+29
| | | | llvm-svn: 132193
* Assorted fixes for Win64 EH unwind info emission:Charles Davis2011-05-271-4/+13
| | | | | | | | | | - Flip order of bitfields. This gets our output matching GAS. - Handle case where the end of the prolog wasn't specified. - If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes. Add a test for the latter two. llvm-svn: 132188
* InstCombine: Make switch folding with equality compares more aggressive by ↵Benjamin Kramer2011-05-271-0/+40
| | | | | | | | trying instsimplify on the arm where we know the compared value. Stuff like "x == y ? y : x&y" now folds into "x&y". llvm-svn: 132185
* Fix PR10029 - VerifyCoalescing failure on patterns_dfa.c of 445.gobmk.Cameron Zwarich2011-05-271-0/+53
| | | | llvm-svn: 132181
* Add a test for Win64 EH unwind information emission.Charles Davis2011-05-271-0/+51
| | | | llvm-svn: 132180
* Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist. Chad Rosier2011-05-263-18/+40
| | | | | | | crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and crc64.[8|16|32] have been renamed to .crc32.64.[8|64]. llvm-svn: 132163
* During branch folding avoid inserting redundant DBG_VALUE machine instructions.Devang Patel2011-05-261-0/+92
| | | | llvm-svn: 132148
* Make few ExecutionEngine tests XFAIL for ARM, since ExecutionEngine is ↵Galina Kistanova2011-05-2615-0/+31
| | | | | | broken for ARM, please remove the following XFAIL when it will be fixed. llvm-svn: 132135
* Add support for C++ exception handling.Akira Hatanaka2011-05-261-8/+8
| | | | llvm-svn: 132131
* Fix test on Windows.Eli Friedman2011-05-261-2/+2
| | | | llvm-svn: 132126
* Add a test for the chained directives that I forgot last time.Charles Davis2011-05-261-0/+3
| | | | llvm-svn: 132110
* Reverting 132105: it broke some LLVM-GCC DejaGNU tests.Stuart Hastings2011-05-261-35/+0
| | | | llvm-svn: 132108
* Test .seh_startchained and .seh_endchained parsing.Charles Davis2011-05-261-0/+3
| | | | | | | | | | | Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with chained unwind areas exposed by the test that were related to this. The ChainedParent field had the wrong address, because when the chained unwind info was added, the addresses shifted around. Now we store the pointers to the structures, which are now allocated from the MC heap. llvm-svn: 132106
* Correctly handle a one-word struct passed byval on x86_64.Stuart Hastings2011-05-261-0/+35
| | | | | | rdar://problem/6920088 llvm-svn: 132105
* indvars: incremental fixes for -disable-iv-rewrite and testcases.Andrew Trick2011-05-261-1/+66
| | | | | | | | Use a proper worklist for use-def traversal without holding onto an iterator. Now that we process all IV uses, we need complete logic for resusing existing derived IV defs. See HoistStep. llvm-svn: 132103
* Rewrite fast-isel integer cast handling to handle more cases, and to be ↵Eli Friedman2011-05-252-7/+79
| | | | | | | | | | simpler and more consistent. The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts). rdar://9437928 . llvm-svn: 132099
* Define WeakRefDirective.Akira Hatanaka2011-05-251-0/+12
| | | | llvm-svn: 132098
* PR9998: ashr exact %x, 31 is not equivalent to sdiv exact %x, -2147483648.Eli Friedman2011-05-251-0/+16
| | | | llvm-svn: 132097
* Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues withCharles Davis2011-05-251-0/+14
| | | | | | | | | | them. I had to add a special SwitchSectionNoChange method to MCStreamer just for .seh_handlerdata. If this isn't OK, please let me know, and I'll find some other way to fix .seh_handlerdata streaming. llvm-svn: 132084
* Implement the 'm' modifier. Note that it only works for memory operands.Eric Christopher2011-05-251-0/+11
| | | | | | Part of rdar://9119939 llvm-svn: 132081
* Custom-lower FCOPYSIGN nodes.Akira Hatanaka2011-05-252-0/+59
| | | | llvm-svn: 132074
* Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix theCharles Davis2011-05-251-0/+6
| | | | | | buggy methods that parse these directives. llvm-svn: 132045
* Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. ThisCameron Zwarich2011-05-251-0/+4
| | | | | | fixes <rdar://problem/9495913> llvm-svn: 132042
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