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* [Hexagon] Enable .cur formation in MISched for Hexagon V60Krzysztof Parzyszek2016-07-181-0/+62
| | | | | | | | | | | Schedule a load and its use in the same packet in MISched. Previously, isResourceAvailable was returning false for dependences in the same packet, which prevented MISched from packetizing a load and its use in the same packet for v60. Patch by Ikhlas Ajbar. llvm-svn: 275804
* Revert "r275571 [DSE]Enhance shorthening MemIntrinsic based on OverlapIntervals"Alexander Kornienko2016-07-182-35/+0
| | | | | | Causes https://llvm.org/bugs/show_bug.cgi?id=28588 llvm-svn: 275801
* [PowerPC] Remove redundant direct moves when extracting integers and ↵Nemanja Ivanovic2016-07-181-0/+107
| | | | | | | | | | | | | | converting to FP This patch corresponds to review: https://reviews.llvm.org/D21354 We use direct moves for extracting integer elements from vectors. We also use direct moves when converting integers to FP. When these operations are chained, we get a direct move out of a VSR followed by a direct move back into a VSR. These are redundant - all we need to do is line up the element and convert. llvm-svn: 275796
* [MC] Cleanup Error Handling in AsmParserNirav Dave2016-07-181-0/+2
| | | | | | | | | | | | | | | Add parseToken and compatriot functions to stitch error checks in straight linear code. As part of this fix some erronous handling of directives where the EndOfStatement token either was not checked or Lexed on termination. Reviewers: rnk, majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22312 llvm-svn: 275795
* [Hexagon] Use timing class info as tie-breaker in machine schedulerKrzysztof Parzyszek2016-07-181-1/+1
| | | | | | Patch by Sirish Pande. llvm-svn: 275794
* [Hexagon] HexagonMachineScheduler should account for resourcesKrzysztof Parzyszek2016-07-181-1/+0
| | | | | | | | | | | | | | | | | The machine scheduler needs to account for available resources more accurately in order to avoid scheduling an instruction that forces a new packet to be created. This occurs in two ways: First, an instruction without an available resource may have a large priority due to other metrics and be scheduled when there are other instructions with available resources. Second, an instruction with a non-zero latency may become available prematurely. In both these cases, we attempt change the priority in order to allow a better instruction to be scheduled. Patch by Brendon Cahoon. llvm-svn: 275793
* [Hexagon] Fix zero latency instructions with multiple predecessorsKrzysztof Parzyszek2016-07-181-0/+1
| | | | | | | | | | | An instruction may have multiple predecessors that are candidates for using .cur. However, only one of them can use .cur in the packet. When this case occurs, we need to make sure that only one of the dependences gets a 0 latency value. Patch by Brendon Cahoon. llvm-svn: 275790
* [SLPVectorizer][X86] Added sqrt vectorization testsSimon Pilgrim2016-07-181-0/+274
| | | | llvm-svn: 275788
* [inlineasm] Propagate operand constraints to the backendSimon Dardis2016-07-181-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | When SelectionDAGISel transforms a node representing an inline asm block, memory constraint information is not preserved. This can cause constraints to be broken when a memory offset is of the form: offset + frame index when the frame is resolved. By propagating the constraints all the way to the backend, targets can enforce memory operands of inline assembly to conform to their constraints. For MIPSR6, some instructions had their offsets reduced to 9 bits from 16 bits such as ll/sc. This becomes problematic when using inline assembly to perform atomic operations, as an offset can generated that is too big to encode in the instruction. Reviewers: dsanders, vkalintris Differential Review: https://reviews.llvm.org/D21615 llvm-svn: 275786
* AMDGPU: Disable AMDGPUPromoteAlloca pass for shader calling conventions.Nicolai Haehnle2016-07-181-0/+29
| | | | | | | | | | | | | | | | Summary: The work item intrinsics are not available for the shader calling conventions. And even if we did hook them up most shader stages haves some extra restrictions on the amount of available LDS. Reviewers: tstellarAMD, arsenm Subscribers: nhaehnle, arsenm, llvm-commits, kzhuravl Differential Revision: https://reviews.llvm.org/D20728 llvm-svn: 275779
* [ARM] Update test to use CHECK-LABEL. NFCI.Diana Picus2016-07-181-6/+8
| | | | llvm-svn: 275777
* [ARM] Skip inline asm memory operands in DAGToDAGISelDiana Picus2016-07-181-0/+11
| | | | | | | | | | | | | | | | | | | | The current logic for handling inline asm operands in DAGToDAGISel interprets the operands by looking for constants, which should represent the flags describing the kind of operand we're dealing with (immediate, memory, register def etc). The operands representing actual data are skipped only if they are non-const, with the exception of immediate operands which are skipped explicitly when a flag describing an immediate is found. The oversight is that memory operands may be const too (e.g. for device drivers reading a fixed address), so we should explicitly skip the operand following a flag describing a memory operand. If we don't, we risk interpreting that constant as a flag, which is definitely not intended. Fixes PR26038 Differential Revision: https://reviews.llvm.org/D22103 llvm-svn: 275776
* [AVX512] Add EVEX versions of scalar ADD/SUB/MUL/DIV to load folding tables.Craig Topper2016-07-181-0/+137
| | | | llvm-svn: 275775
* [X86] Fix test checks to include leading 'v' on avx mnemonic names.Craig Topper2016-07-181-13/+13
| | | | llvm-svn: 275774
* [ARM] Honour ABI for rem under -O0 for EABI, GNUEABI, Android and MuslDiana Picus2016-07-181-12/+105
| | | | | | | | | | | | | | | | | | | | At higher optimization levels, we generate the libcall for DIVREM_Ix, which is fine: aeabi_{u|i}divmod. At -O0 we generate the one for REM_Ix, which is the default {u}mod{q|h|s|d}i3. This commit makes sure that we don't generate REM_Ix calls for ABIs that don't support them (i.e. where we need to use DIVREM_Ix instead). This is achieved by bailing out of FastISel, which can't handle non-double multi-reg returns, and letting the legalization infrastructure expand the REM_Ix calls. It also updates the divmod-eabi.ll test to run under -O0 as well, and adds some Windows checks to it to make sure we don't break things for it. Fixes PR27068 Differential Revision: https://reviews.llvm.org/D21926 llvm-svn: 275773
* [X86] Add VPADD instructions to X86InstrInfo::isAssociativeAndCommutative.Craig Topper2016-07-188-436/+458
| | | | llvm-svn: 275769
* [X86] Add floating point packed logical ops to ↵Craig Topper2016-07-182-3/+3
| | | | | | X86InstrInfo::isAssociativeAndCommutative. llvm-svn: 275768
* [X86] Add AVX512 instructions to X86InstrInfo::isAssociativeAndCommutative.Craig Topper2016-07-181-276/+276
| | | | llvm-svn: 275767
* [X86] Add AVX512 load opcodes and a couple AVX load opcodes to ↵Craig Topper2016-07-182-22/+22
| | | | | | X86InstrInfo::areLoadsFromSameBasePtr. llvm-svn: 275765
* [X86] Add more opcodes to isFrameLoadOpcode/isFrameStoreOpcode. Mainly ↵Craig Topper2016-07-186-144/+144
| | | | | | AVX-512 related. llvm-svn: 275764
* [AVX512] Use VMOVAPSZ128rr/VMOVAPS256rr for VR128X/VR256X physreg moves when ↵Craig Topper2016-07-1813-354/+381
| | | | | | | | VLX is supported. Ideally we would use VEX encoded moves instead of EVEX if the high 16 registers aren't referenced, but this a good first step. llvm-svn: 275763
* [GVNHoist] Change the key for VNtoInsns to a pairDavid Majnemer2016-07-181-4/+4
| | | | | | | | | | | | | | | | | | | | | While debugging GVNHoist, I found it confusing that the entries in a VNtoInsns were not always value numbers. They _usually_ were except for StoreInst in which case they were a hash of two different value numbers. This leads to two observations: - It is more difficult to debug things when the semantic contents of VNtoInsns changes over time. - Using a single value number is not much cheaper, the value of VNtoInsns is a SmallVector. - It is not immediately clear what the algorithm would do if there were hash collisions in the StoreInst case. Using a DenseMap of std::pair sidesteps all of this. N.B. The changes in the test were due their sensitivity to the iteration order of VNtoInsns which has changed. llvm-svn: 275761
* [llvm-cov] Attempt to fix a test failure on WindowsVedant Kumar2016-07-181-2/+2
| | | | | | | | | | | | | | | Don't make the test/tools/llvm-cov/demangle.test depend on the order in which symbols are seen, or on the exact formatting llvm-cov emits after a symbol is printed. This is an attempt to fix a Windows bot failure: http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/9141 I don't know what the root cause of the failure is, or why the showTemplateInstantiations test doesn't fail in the same way on the Windows bots. However, this measure can't hurt, and it'll at least get me on the blamelists again. llvm-svn: 275758
* Revert r275678, "Revert "Revert r275027 - Let FuncAttrs infer the 'returned' ↵NAKAMURA Takumi2016-07-183-6/+6
| | | | | | | | | | argument attribute"" This reverts also r275029, "Update Clang tests after adding inference for the returned argument attribute" It broke LTO build. Seems miscompilation. llvm-svn: 275756
* [GVN] Move other PRE tests to a subdirectory.Davide Italiano2016-07-175-0/+0
| | | | llvm-svn: 275742
* [GVN] Move the PRE/LOADPRE test in a subdirectory.Davide Italiano2016-07-1718-0/+0
| | | | llvm-svn: 275741
* [GVN] Use FileCheck instead of grep for tests.Davide Italiano2016-07-1718-19/+135
| | | | llvm-svn: 275739
* [X86] Add CTPOP/CTLZ/CTTZ scalar cost testsSimon Pilgrim2016-07-171-6/+171
| | | | llvm-svn: 275725
* [X86][AVX] Added VBROADCASTF128/VBROADCASTI128 testsSimon Pilgrim2016-07-172-0/+240
| | | | llvm-svn: 275713
* [X86] Regenerated ctlz/cttz scalar tests for 32/64-bit targets with/without ↵Simon Pilgrim2016-07-171-170/+640
| | | | | | LZCNT/TZCNT support llvm-svn: 275710
* [X86] Regenerated popcnt scalar tests for 32/64-bit targets with/without ↵Simon Pilgrim2016-07-171-13/+230
| | | | | | POPCNT support llvm-svn: 275709
* [ThinLTO] Perform profile-guided indirect call promotionTeresa Johnson2016-07-172-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: To enable profile-guided indirect call promotion in ThinLTO mode, we simply add call graph edges for each profitable target from the profile to the summaries, then the summary-guided importing will consider the callee for importing as usual. Also we need to enable the indirect call promotion pass creation in the PassManagerBuilder when PerformThinLTO=true (we are in the ThinLTO backend), so that the newly imported functions are considered for promotion in the backends. The IC promotion profiles refer to callees by GUID, which required adding GUIDs to the per-module VST in bitcode (and assigning them valueIds similar to how they are assigned valueIds in the combined index). Reviewers: mehdi_amini, xur Subscribers: mehdi_amini, davidxl, llvm-commits Differential Revision: http://reviews.llvm.org/D21932 llvm-svn: 275707
* X86: Updated a test file. NFC.Elena Demikhovsky2016-07-171-79/+452
| | | | | | | This test shows subotimal code generated for AVX-512 vs PENTIUM4. The issue will be fixed in an upcomming commit. llvm-svn: 275702
* [PM] Convert IVUsers analysis to new pass manager.Dehao Chen2016-07-161-0/+1
| | | | | | | | | | | | Summary: Convert IVUsers analysis to new pass manager. Reviewers: davidxl, silvas Subscribers: junbuml, sanjoy, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D22434 llvm-svn: 275698
* [InstCombine] allow X + signbit --> X ^ signbit for vector splatsSanjay Patel2016-07-161-1/+1
| | | | llvm-svn: 275691
* add vector test to show missing transformSanjay Patel2016-07-161-0/+10
| | | | llvm-svn: 275690
* update tests to use FileCheck, consolidate tests, fix commentsSanjay Patel2016-07-163-80/+106
| | | | llvm-svn: 275688
* update test to use FileCheckSanjay Patel2016-07-161-5/+10
| | | | llvm-svn: 275687
* auto-generate checksSanjay Patel2016-07-161-47/+54
| | | | llvm-svn: 275686
* auto-ggenerate checksSanjay Patel2016-07-161-42/+47
| | | | llvm-svn: 275685
* [InstCombine] reassociate logic ops with constants separated by a zextSanjay Patel2016-07-161-15/+10
| | | | | | | | | | | | This is a partial implementation of a general fold for associative+commutative operators: (op (cast (op X, C2)), C1) --> (cast (op X, op (C1, C2))) (op (cast (op X, C2)), C1) --> (op (cast X), op (C1, C2)) There are 7 associative operators and 13 cast types, so this could potentially go a lot further. Differential Revision: https://reviews.llvm.org/D22421 llvm-svn: 275684
* Revert "Revert r275027 - Let FuncAttrs infer the 'returned' argument attribute"Hal Finkel2016-07-163-6/+6
| | | | | | | | | | | | | | | | This reverts commit r275042; the initial commit triggered self-hosting failures on ARM/AArch64. James Molloy identified the problematic backend code, which has been disabled in r275677. Trying again... Original commit message: Let FuncAttrs infer the 'returned' argument attribute A function can have one argument with the 'returned' attribute, indicating that the associated argument is always the return value of the function. Add FuncAttrs inference logic. llvm-svn: 275678
* Disable this-return argument forwarding on ARM/AArch64Hal Finkel2016-07-163-5/+5
| | | | | | | | | | | r275042 reverted function-attribute inference for the 'returned' attribute because the feature triggered self-hosting failures on ARM and AArch64. James Molloy determined that the this-return argument forwarding feature, which directly ties the returned input argument to the returned value, was the cause. It seems likely that this forwarding code contains, or triggers, a subtle bug. Disabling for now until we can track that down. llvm-svn: 275677
* Re-commit [AMDGPU] Add metadata for runtimeYaxun Liu2016-07-161-0/+848
| | | | | | Attempting to fix lit test failure on ppc. llvm-svn: 275676
* llc: Add support for -run-pass noneMatthias Braun2016-07-16174-174/+174
| | | | | | | | | | This does not schedule any passes besides the ones necessary to construct and print the machine function. This is useful to test .mir file reading and printing. Differential Revision: http://reviews.llvm.org/D22432 llvm-svn: 275664
* ARM/MIR: Move test from MIR to CodeGen/ARM directoryMatthias Braun2016-07-161-1/+1
| | | | | | | | | | test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir is an actual test for the ARM load store optimization pass and not a test of the mir parser/printer. It belongs to test/CodeGen/ARM; This also updates the test to use the new -run-pass llc syntax. llvm-svn: 275662
* MIParser: reject subregister indexes on physregsMatthias Braun2016-07-161-0/+12
| | | | llvm-svn: 275658
* [llvm-cov] Optionally use a symbol demangler when preparing reportsVedant Kumar2016-07-151-0/+4
| | | | | | | | | | Add an option to specify a symbol demangler (as well as options to the demangler). This can be used to make reports more human-readable. This option is especially useful in -output-dir mode, since it isn't as easy to manually pipe reports into a demangler in this mode. llvm-svn: 275640
* AMDGPU: Fix verifier error from partially undef copyMatt Arsenault2016-07-151-3/+67
| | | | | | | | | | | | | | In this situation: %VGPR2<def> = BUFFER_LOAD_DWORD_OFFSET %SGPR8_SGPR9_SGPR10_SGPR11, %VGPR7<def,tied3> = V_MAC_F32_e32 %VGPR0<undef>, %VGPR1<kill>, %VGPR7<kill,tied0>, %EXEC<imp-use> %VGPR3_VGPR4_VGPR5_VGPR6<def> = COPY %VGPR0_VGPR1_VGPR2_VGPR3 %VGPR4<def> = COPY %VGPR2 The copy for VGPR1 -> VGPR4 was an error from reading undefined VGPR1, but VGPR4 is defined immediately after this copy. llvm-svn: 275635
* ExpandPostRAPseudos should transfer implicit uses, not only implicit defsMichael Kuperstein2016-07-152-0/+14
| | | | | | | | | | | | | | | | | | | Previously, we would expand: %BL<def> = COPY %DL<kill>, %EBX<imp-use,kill>, %EBX<imp-def> Into: %BL<def> = MOV8rr %DL<kill>, %EBX<imp-def> Dropping the imp-use on the floor. That confused CriticalAntiDepBreaker, which (correctly) assumes that if an instruction defs but doesn't use a register, that register is dead immediately before the instruction - while in this case, the high lanes of EBX can be very much alive. This fixes PR28560. Differential Revision: https://reviews.llvm.org/D22425 llvm-svn: 275634
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