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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-18 14:52:13 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-18 14:52:13 +0000 |
| commit | 3467e9d0a93db2d0a997168d2231d6860b010784 (patch) | |
| tree | eafeb1133dfa780f2a2560db262bf0b5dab94a25 /llvm/test | |
| parent | ab1b926bb9033018ace8d1dbe780ac954659a94b (diff) | |
| download | bcm5719-llvm-3467e9d0a93db2d0a997168d2231d6860b010784.tar.gz bcm5719-llvm-3467e9d0a93db2d0a997168d2231d6860b010784.zip | |
[Hexagon] HexagonMachineScheduler should account for resources
The machine scheduler needs to account for available resources
more accurately in order to avoid scheduling an instruction that
forces a new packet to be created.
This occurs in two ways: First, an instruction without an available
resource may have a large priority due to other metrics and be
scheduled when there are other instructions with available resources.
Second, an instruction with a non-zero latency may become available
prematurely. In both these cases, we attempt change the priority
in order to allow a better instruction to be scheduled.
Patch by Brendon Cahoon.
llvm-svn: 275793
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll index 3edf1e35d21..6fb0a3e2658 100644 --- a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll +++ b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll @@ -1,4 +1,3 @@ -; XFAIL: * ; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx-double \ ; RUN: -hexagon-bit=0 < %s | FileCheck %s |
