summaryrefslogtreecommitdiffstats
path: root/llvm/test
Commit message (Collapse)AuthorAgeFilesLines
* [SystemZ] Try to fold shifts into TMxxRichard Sandiford2013-09-132-0/+80
| | | | | | E.g. "SRL %r2, 2; TMLL %r2, 1" => "TMLL %r2, 4". llvm-svn: 190672
* AArch64: use RegisterOperand for NEON registers.Tim Northover2013-09-132-6/+11
| | | | | | | | | | | | | | | | Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). llvm-svn: 190665
* Add initial support for handling gnu style pubnames accepted by someEric Christopher2013-09-131-0/+126
| | | | | | | | versions of gold. This support is designed to allow gold to produce gdb_index sections similar to the accelerator tables and consumable by gdb. llvm-svn: 190649
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-121-0/+16
| | | | llvm-svn: 190644
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-121-0/+18
| | | | | | | This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643
* Remove unnecessary TBAA metadata from r190636's test caseHal Finkel2013-09-121-13/+9
| | | | llvm-svn: 190637
* Fix PPC ABI for ByVal structs with vector membersHal Finkel2013-09-121-0/+64
| | | | | | | | | | When a structure is passed by value, and that structure contains a vector member, according to the PPC ABI, the structure will receive enhanced alignment (so that the vector within the structure will always be aligned). This should resolve PR16641. llvm-svn: 190636
* Patch provide by Tom Roeder!Joe Abbey2013-09-121-0/+9
| | | | | | | | | | | Reviewed by Joe Abbey and Tobias Grosser Here is a patch that fixes decoding of CE_SELECT in BitcodeReader, along with a simple test case. The problem in the current code is that it generates but doesn't accept bitcode that uses vectors for the first element of a select in this context. llvm-svn: 190634
* Make the PPC fast-math sqrt expansion safe at 0Hal Finkel2013-09-121-1/+4
| | | | | | | | | | | In fast-math mode sqrt(x) is calculated using the fast expansion of the reciprocal of the reciprocal sqrt expansion. The reciprocal and reciprocal sqrt expansions use the associated estimate instructions along with some Newton iterations. Unfortunately, as a result, sqrt(0) was being calculated as NaN, which is not correct. Now we explicitly return a result of zero if the input is zero. llvm-svn: 190624
* Implement asm support for a few PowerPC bookIII that are needed for assemblingRoman Divacky2013-09-121-0/+107
| | | | | | FreeBSD kernel. llvm-svn: 190618
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-122-0/+14
| | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611
* Mark PPC MFTB and DST (and friends) as deprecatedHal Finkel2013-09-121-0/+12
| | | | | | | | Use the new instruction deprecation feature to mark mftb (now replaced with mfspr) and dst (along with the other Altivec cache control instructions) as deprecated when targeting cores supporting at least ISA v2.03. llvm-svn: 190605
* Somehow this important part of the patch, where I actually check the Mask,Joey Gouly2013-09-121-3/+6
| | | | | | | | got lost during my iterations of review. Thanks to Hal for spotting it! llvm-svn: 190604
* LLVM interpreter: added a test for insert- extract- valueElena Demikhovsky2013-09-121-0/+21
| | | | llvm-svn: 190600
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-123-4/+49
| | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. llvm-svn: 190595
* PPC: Enable aggressive anti-dependency breakingHal Finkel2013-09-122-14/+15
| | | | | | | | | | | | | | | | | | | | Aggressive anti-dependency breaking is enabled by default for all PPC cores. This provides a general speedup on the P7 and other platforms (among other factors, the instruction group formation for the non-embedded PPC cores is done during post-RA scheduling). In order to do this safely, the incompatibility between uses of the MFOCRF instruction and anti-dependency breaking are resolved by marking MFOCRF with hasExtraSrcRegAllocReq. As noted in the removed FIXME, the problem was that MFOCRF's output is sensitive to the identify of the source register, and always paired with a shift to undo this effect. Because anti-dependency breaking is unaware of this hidden dependency of the shift amount on the source register of the MFOCRF instruction, changing that register must be inhibited. Two test cases were adjusted: The SjLj test was made more insensitive to register choices and scheduling; the saveCR test disabled anti-dependency breaking because part of what it is testing is proper register reuse. llvm-svn: 190587
* R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedbackTom Stellard2013-09-121-0/+44
| | | | | | | | | | | | | For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist. The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take a resource descriptor might be nicer. The maximum number of input SGPRs is bumped to 17. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190575
* Implement TTI getUnrollingPreferences for PowerPCHal Finkel2013-09-112-0/+52
| | | | | | | | The PowerPC A2 core greatly benefits from aggressive concatenation unrolling; use the new getUnrollingPreferences to enable this by default when targeting the PPC A2 core. llvm-svn: 190549
* Try to fix the atom buildbots by adding an explicit 'cpu' to the 'llc' command.Bill Wendling2013-09-112-5/+5
| | | | llvm-svn: 190541
* [mips][msa] Added test cases that were supposed to be part of r190507, ↵Daniel Sanders2013-09-113-0/+734
| | | | | | r190509, r190512, and r190518. llvm-svn: 190522
* [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv ↵Daniel Sanders2013-09-112-0/+323
| | | | | | from normal IR (i.e. not intrinsics) llvm-svn: 190518
* [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, ↵Daniel Sanders2013-09-112-0/+224
| | | | | | fsqrt, and fsub from normal IR (i.e. not intrinsics) llvm-svn: 190512
* [mips][msa] Added support for matching div_[su] from normal IR (i.e. not ↵Daniel Sanders2013-09-111-0/+130
| | | | | | intrinsics) llvm-svn: 190509
* [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-111-0/+68
| | | | | | The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection. llvm-svn: 190507
* [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsicsDaniel Sanders2013-09-111-52/+86
| | | | | | | The elements of the operands should be half the width of the elements of the result. llvm-svn: 190505
* Teach loop-idiom about address space pointer sizesMatt Arsenault2013-09-115-0/+360
| | | | llvm-svn: 190491
* Fix missing CHECK-LABELsMatt Arsenault2013-09-101-5/+5
| | | | llvm-svn: 190426
* Teach ScalarEvolution about pointer address spacesMatt Arsenault2013-09-101-0/+68
| | | | llvm-svn: 190425
* [SystemZ] Add TM and TMYRichard Sandiford2013-09-104-0/+368
| | | | | | | | | | | | | | | | | | | | | | | The main complication here is that TM and TMY (the memory forms) set CC differently from the register forms. When the tested bits contain some 0s and some 1s, the register forms set CC to 1 or 2 based on the value the uppermost bit. The memory forms instead set CC to 1 regardless of the uppermost bit. Until now, I've tried to make it so that a branch never tests for an impossible CC value. E.g. NR only sets CC to 0 or 1, so branches on the result will only test for 0 or 1. Originally I'd tried to do the same thing for TM and TMY by using custom matching code in ISelDAGToDAG. That ended up being very ugly though, and would have meant duplicating some of the chain checks that the common isel code does. I've therefore gone for the simpler alternative of adding an extra operand to the TM DAG opcode to say whether a memory form would be OK. This means that the inverse of a "TM;JE" is "TM;JNE" rather than the more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE". I suppose that's arguably less confusing though... llvm-svn: 190400
* [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)Daniel Sanders2013-09-101-44/+0
| | | | | | The dotp_[su].b instructions never existed in any revision of the MSA spec. llvm-svn: 190398
* Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of ↵Vladimir Medic2013-09-101-0/+4
| | | | | | register when PFU is 32 bit. llvm-svn: 190397
* MCObjectFileInfo.cpp: Fix a couple of possible typo(s), ↵NAKAMURA Takumi2013-09-101-3/+0
| | | | | | | | s/DwarfPub/DwarfGnuPub/, in r190344. XFAIL can be removed. (in r190374) llvm-svn: 190386
* llvm/test/DebugInfo/dwarf-public-names.ll: Mark it as XFAIL for PECOFF ↵NAKAMURA Takumi2013-09-101-0/+3
| | | | | | | targets, for now. Investigating. FIXME: llvm-dwarfdump doesn't handle PECOFF. llvm-svn: 190374
* Debug Info: In DIBuilder, the context fields of a TAG_inheritance and aManman Ren2013-09-093-0/+178
| | | | | | | | TAG_friend are updated to use scope reference. Added testing cases to verify that class with inheritance can be uniqued. llvm-svn: 190364
* Don't shrink atomic ops to bool in GlobalOpt.Eli Friedman2013-09-091-0/+15
| | | | | | | | | LLVM IR doesn't currently allow atomic bool load/store operations, and the transformation is dubious anyway because it isn't profitable on all platforms. PR17163. llvm-svn: 190357
* [InstCombiner] Expose opportunities to merge subtract and comparison.Quentin Colombet2013-09-091-0/+65
| | | | | | | | | | | | | | | | | | | | | Several architectures use the same instruction to perform both a comparison and a subtract. The instruction selection framework does not allow to consider different basic blocks to expose such fusion opportunities. Therefore, these instructions are “merged” by CSE at MI IR level. To increase the likelihood of CSE to apply in such situation, we reorder the operands of the comparison, when they have the same complexity, so that they matches the order of the most frequent subtract. E.g., icmp A, B ... sub B, A <rdar://problem/14514580> llvm-svn: 190352
* Debug Info Testing: remove a commented out line.Manman Ren2013-09-091-1/+0
| | | | llvm-svn: 190351
* Another attempt to fix windows buildbots.Bill Wendling2013-09-092-2/+2
| | | | llvm-svn: 190350
* Attempt to fix buildbots by giving an explicit output to the llvm-mc command.Bill Wendling2013-09-092-2/+2
| | | | llvm-svn: 190349
* Expand test to make sure that we can generate compact unwind from an ASM file.Bill Wendling2013-09-091-6/+13
| | | | llvm-svn: 190348
* Expand test to make sure that we can generate compact unwind from an ASM file.Bill Wendling2013-09-091-1/+9
| | | | llvm-svn: 190347
* Debug Info: Use DIScopeRef for DIType::getContext.Manman Ren2013-09-092-0/+141
| | | | | | | | | | | | | | | | | In DIBuilder, the context field of a TAG_member is updated to use the scope reference. Verifier is updated accordingly. DebugInfoFinder now needs to generate a type identifier map to have access to the actual scope. Same applies for BreakpointPrinter. processModule of DebugInfoFinder is called during initialization phase of the verifier to make sure the type identifier map is constructed early enough. We are now able to unique a simple class as demonstrated by the added testing case. llvm-svn: 190334
* Revert patches to add case-range support for PR1255.Bob Wilson2013-09-094-65/+99
| | | | | | | | | | | | | | | | | The work on this project was left in an unfinished and inconsistent state. Hopefully someone will eventually get a chance to implement this feature, but in the meantime, it is better to put things back the way the were. I have left support in the bitcode reader to handle the case-range bitcode format, so that we do not lose bitcode compatibility with the llvm 3.3 release. This reverts the following commits: 155464, 156374, 156377, 156613, 156704, 156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575, 157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884, 157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100, 159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659, 159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736 llvm-svn: 190328
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-0910-2/+289
| | | | | | | | | IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
* XCore handling of thread local loweringRobert Lytton2013-09-091-16/+55
| | | | | | | | | | | Fix XCoreLowerThreadLocal trying to initialise globals which have no initializer. Add handling of const expressions containing thread local variables. These need to be replaced with instructions, as the thread ID is used to access the thread local variable. llvm-svn: 190300
* XCore target: change to Sched::SourceRobert Lytton2013-09-091-0/+25
| | | | | | | This sidesteps a bug in PrescheduleNodesWithMultipleUses() which does not check if callResources will be affected by the transformation. llvm-svn: 190299
* XCore target: fix weak linkage attribute handlingRobert Lytton2013-09-091-0/+17
| | | | llvm-svn: 190298
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-11/+15
| | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> llvm-svn: 190290
* Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the ↵Jiangning Liu2013-09-094-0/+3316
| | | | | | | | following 26 instructions, SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL llvm-svn: 190288
OpenPOWER on IntegriCloud