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authorHal Finkel <hfinkel@anl.gov>2013-09-12 23:20:06 +0000
committerHal Finkel <hfinkel@anl.gov>2013-09-12 23:20:06 +0000
commit262a224712e1c4f2bfb674e5f6038db83649ccb8 (patch)
tree095a27e6d87487a09ed6f805981d7dc05be9c7eb /llvm/test
parent4ef077a072f652df7d0664f65fefeb4cfd856dd3 (diff)
downloadbcm5719-llvm-262a224712e1c4f2bfb674e5f6038db83649ccb8.tar.gz
bcm5719-llvm-262a224712e1c4f2bfb674e5f6038db83649ccb8.zip
Fix PPC ABI for ByVal structs with vector members
When a structure is passed by value, and that structure contains a vector member, according to the PPC ABI, the structure will receive enhanced alignment (so that the vector within the structure will always be aligned). This should resolve PR16641. llvm-svn: 190636
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/PowerPC/vec-abi-align.ll64
1 files changed, 64 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vec-abi-align.ll b/llvm/test/CodeGen/PowerPC/vec-abi-align.ll
new file mode 100644
index 00000000000..3d6129bc2fa
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vec-abi-align.ll
@@ -0,0 +1,64 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.s2 = type { i64, <4 x float> }
+
+@ve = external global <4 x float>
+@n = external global i64
+
+; Function Attrs: nounwind
+define void @test1(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, <4 x float> inreg %vs.coerce) #0 {
+entry:
+ store <4 x float> %vs.coerce, <4 x float>* @ve, align 16, !tbaa !0
+ ret void
+
+; CHECK-LABEL: @test1
+; CHECK: stvx 2,
+; CHECK: blr
+}
+
+; Function Attrs: nounwind
+define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval nocapture readonly %vs) #0 {
+entry:
+ %m = getelementptr inbounds %struct.s2* %vs, i64 0, i32 0
+ %0 = load i64* %m, align 8, !tbaa !2
+ store i64 %0, i64* @n, align 8, !tbaa !2
+ %v = getelementptr inbounds %struct.s2* %vs, i64 0, i32 1
+ %1 = load <4 x float>* %v, align 16, !tbaa !0
+ store <4 x float> %1, <4 x float>* @ve, align 16, !tbaa !0
+ ret void
+
+; CHECK-LABEL: @test2
+; CHECK: ld {{[0-9]+}}, 112(1)
+; CHECK: li [[REG16:[0-9]+]], 16
+; CHECK: addi [[REGB:[0-9]+]], 1, 112
+; CHECK: lvx 2, [[REGB]], [[REG16]]
+; CHECK: blr
+}
+
+; Function Attrs: nounwind
+define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval nocapture readonly %vs) #0 {
+entry:
+ %m = getelementptr inbounds %struct.s2* %vs, i64 0, i32 0
+ %0 = load i64* %m, align 8, !tbaa !2
+ store i64 %0, i64* @n, align 8, !tbaa !2
+ %v = getelementptr inbounds %struct.s2* %vs, i64 0, i32 1
+ %1 = load <4 x float>* %v, align 16, !tbaa !0
+ store <4 x float> %1, <4 x float>* @ve, align 16, !tbaa !0
+ ret void
+
+; CHECK-LABEL: @test3
+; CHECK: ld {{[0-9]+}}, 128(1)
+; CHECK: li [[REG16:[0-9]+]], 16
+; CHECK: addi [[REGB:[0-9]+]], 1, 128
+; CHECK: lvx 2, [[REGB]], [[REG16]]
+; CHECK: blr
+}
+
+attributes #0 = { nounwind }
+
+!0 = metadata !{metadata !"omnipotent char", metadata !1}
+!1 = metadata !{metadata !"Simple C/C++ TBAA"}
+!2 = metadata !{metadata !"long", metadata !0}
+
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