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* AArch64: use correct SDValue # when looking for bitfield placement.Tim Northover2016-07-051-0/+36
| | | | | | | | | | The other use really does only care about the SDNode (it checks the opcode against a whitelist), but bitFieldPlacement can be misled if the node produces multiple results. Patch by Ismail Badawi. llvm-svn: 274567
* AMDGPU: Fix folding SGPRs into madak/madmk src0Matt Arsenault2016-07-051-0/+29
| | | | | | | | | | Because of the special immediate operand, the constant bus is already used so SGPRs are never useful. r263212 changed the name of the immediate operand, which broke the verifier check for the restriction. llvm-svn: 274564
* [AMDGPU] Assembler: Fix parsing error with floating-point literals passed to ↵Sam Kolton2016-07-052-0/+18
| | | | | | | | integer instructions Differential Revision: http://reviews.llvm.org/D21972 llvm-svn: 274551
* [X86][AVX512] Autoupgrade the BROADCAST intrinsicsSimon Pilgrim2016-07-056-343/+347
| | | | llvm-svn: 274550
* [X86][AVX512BW] Added BROADCAST intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-052-0/+364
| | | | llvm-svn: 274545
* [Thumb] Reapply r272251 with a fix for PR28348 (mk 2)James Molloy2016-07-052-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | The important thing I was missing was ensuring newly added constants were kept in topological order. Repositioning the node is correct if the constant is newly added (so it has no topological ordering) but wrong if it already existed - positioning it next in the worklist would break the topological ordering. Original commit message: [Thumb] Select a BIC instead of AND if the immediate can be encoded more optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 274543
* [X86][AVX512] Added BROADCAST intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-052-18/+795
| | | | llvm-svn: 274537
* [PowerPC] - Legalize vector types by widening instead of integer promotionNemanja Ivanovic2016-07-055-46/+82
| | | | | | | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D20443 It changes the legalization strategy for illegal vector types from integer promotion to widening. This only applies for vectors with elements of width that is a multiple of a byte since we have hardware support for vectors with 1, 2, 3, 8 and 16 byte elements. Integer promotion for vectors is quite expensive on PPC due to the sequence of breaking apart the vector, extending the elements and reconstituting the vector. Two of these operations are expensive. This patch causes between minor and major improvements in performance on most benchmarks. There are very few benchmarks whose performance regresses. These regressions can be handled in a subsequent patch with a DAG combine (similar to how this patch handles int -> fp conversions of illegal vector types). llvm-svn: 274535
* [X86][AVX512] Added VSHUFPD intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-051-0/+52
| | | | llvm-svn: 274534
* [X86][AVX512VL] Added VSHUFPD/VSHUFPS intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-051-0/+274
| | | | llvm-svn: 274533
* test: relax the match on the timestampSaleem Abdulrasool2016-07-051-1/+1
| | | | llvm-svn: 274529
* Object: support empty UID/GID fieldsSaleem Abdulrasool2016-07-052-0/+5
| | | | | | | | | Normal archives do not have empty UID/GID fields. However, the Microsoft Import library format is a customized archive (it just uses an alternate symbol index format). When the import library is constructed by lib.exe, the UID and GID fields are left empty. Do not abort on such an input. llvm-svn: 274528
* [X86][AVX512] Add support for lowering shuffles to VSHUFPDSimon Pilgrim2016-07-042-8/+3
| | | | llvm-svn: 274520
* Revert "[Thumb] Reapply r272251 with a fix for PR28348"James Molloy2016-07-042-29/+0
| | | | | | This reverts commit r274510 - it made green dragon unhappy. llvm-svn: 274512
* [Thumb] Reapply r272251 with a fix for PR28348James Molloy2016-07-042-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | We were using DAG->getConstant instead of DAG->getTargetConstant. This meant that we could inadvertently increase the use count of a constant if stars aligned, which it did in this testcase. Increasing the use count of the constant could cause ISel to fall over (because DAGToDAG lowering assumed the constant had only one use!) Original commit message: [Thumb] Select a BIC instead of AND if the immediate can be encoded more optimally negated If an immediate is only used in an AND node, it is possible that the immediate can be more optimally materialized when negated. If this is the case, we can negate the immediate and use a BIC instead; int i(int a) { return a & 0xfffffeec; } Used to produce: ldr r1, [CONSTPOOL] ands r0, r1 CONSTPOOL: 0xfffffeec And now produces: movs r1, #255 adds r1, #20 ; Less costly immediate generation bics r0, r1 llvm-svn: 274510
* [X86][AVX512] Autoupgrade the VPERMPD/VPERMQ intrinsicsSimon Pilgrim2016-07-044-85/+86
| | | | llvm-svn: 274506
* [X86][AVX512] Added VPERMPD/VPERMQ intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-042-0/+252
| | | | llvm-svn: 274503
* [X86][AVX512] Autoupgrade the VPERMILPD/VPERMILPS intrinsicsSimon Pilgrim2016-07-044-136/+136
| | | | llvm-svn: 274498
* [X86][AVX512] Added VPERMILPD/VPERMILPS intrinsics fast-isel generic IR testsSimon Pilgrim2016-07-041-0/+163
| | | | | | Added PSHUFD tests as well llvm-svn: 274493
* Add writeonly IR attributeNicolai Haehnle2016-07-0410-22/+60
| | | | | | | | | | | | | | | | | Summary: This complements the earlier addition of IntrWriteMem and IntrWriteArgMem LLVM intrinsic properties, see D18291. Also start using the attribute for memset, memcpy, and memmove intrinsics, and remove their special-casing in BasicAliasAnalysis. Reviewers: reames, joker.eph Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D18714 llvm-svn: 274485
* [CodeGen] Make the code that detects a if a shuffle is really a ↵Craig Topper2016-07-041-6/+0
| | | | | | | | | | concatenation of the inputs more general purpose. We can now handle concatenation of each source multiple times. The previous code just checked for each source to appear once in either order. This also now handles an entire source vector sized piece having undef indices correctly. We now concat with UNDEF instead of using one of the sources. This is responsible for the test case change. llvm-svn: 274483
* [X86][AVX512] Add support for 512-bit shuffle lowering to VPERMPD/VPERMQSimon Pilgrim2016-07-031-75/+39
| | | | llvm-svn: 274473
* [CodeGen] Teach OR combine of shuffles involving zero vectors to better ↵Craig Topper2016-07-031-6/+2
| | | | | | | | handle undef indices. Undef indices can now be treated as zeros. Or if its undef ORed with zero, we will keep the undef. llvm-svn: 274472
* [X86] Add tests to show that the DAG combine for OR of shuffles with zero ↵Craig Topper2016-07-031-0/+28
| | | | | | vectors doesn't handle undefs as well as it could. Fix coming in another commit. llvm-svn: 274471
* [MBB] add a missing corner case in UpdateTerminator()Haicheng Wu2016-07-031-0/+57
| | | | | | | | | | After the block placement, if a block ends with a conditional branch, but the next block is not its successor. The conditional branch should be changed to unconditional branch. This patch fixes PR28307, PR28297, PR28402. Differential Revision: http://reviews.llvm.org/D21811 llvm-svn: 274470
* [X86][AVX512] Add support for VPERMPD/VPERMQ masked shuffle commentsSimon Pilgrim2016-07-032-8/+8
| | | | llvm-svn: 274469
* [X86][AVX512] Add support for 512-bit shuffle decoding of VPERMPD/VPERMQSimon Pilgrim2016-07-031-6/+6
| | | | llvm-svn: 274468
* [X86][AVX512] Add support for VPALIGNR/PSHUFD/PSHUFHW/PSHUFLW masked shuffle ↵Simon Pilgrim2016-07-034-30/+30
| | | | | | comments llvm-svn: 274466
* [InstCombine] enable vector select of bools -> logic foldsSanjay Patel2016-07-031-8/+11
| | | | llvm-svn: 274465
* [X86][AVX512] Add support for UNPCK masked shuffle commentsSimon Pilgrim2016-07-036-75/+75
| | | | llvm-svn: 274464
* [X86][AVX512] Add support for VPERM/VSHUF masked shuffle commentsSimon Pilgrim2016-07-036-66/+66
| | | | llvm-svn: 274462
* [X86][AVX512] Add support for PMOVZX masked shuffle commentsSimon Pilgrim2016-07-035-74/+74
| | | | llvm-svn: 274461
* add vector bool select tests and regenerate checks for scalar bool select testsSanjay Patel2016-07-031-59/+139
| | | | llvm-svn: 274460
* [X86][AVX512] Add support for masked shuffle commentsSimon Pilgrim2016-07-035-58/+58
| | | | | | | | | | This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments. This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course. Differential Revision: http://reviews.llvm.org/D21953 llvm-svn: 274459
* [X86][AVX512] Add support for lowering shuffles to VPERMILPSSimon Pilgrim2016-07-031-0/+27
| | | | llvm-svn: 274458
* Remove dead TLI arg of isKnownNonNull and propagate deadness. NFC.Sean Silva2016-07-022-2/+2
| | | | | | | | | | | | | | This actually uncovered a surprisingly large chain of ultimately unused TLI args. From what I can gather, this argument is a remnant of when isKnownNonNull would look at the TLI directly. The current approach seems to be that InferFunctionAttrs runs early in the pipeline and uses TLI to annotate the TLI-dependent non-null information as return attributes. This also removes the dependence of functionattrs on TLI altogether. llvm-svn: 274455
* [PM] Port LoopAccessInfo analysis to new PMXinliang David Li2016-07-0221-1/+22
| | | | | | | It is implemented as a LoopAnalysis pass as discussed and agreed upon. llvm-svn: 274452
* [X86][AVX512] Add support for lowering shuffles to VPERMILPDSimon Pilgrim2016-07-021-52/+26
| | | | llvm-svn: 274450
* [X86][AVX512VL] Add fast-isel MOVDDUP/MOVSLDUP/MOVSHDUP shuffle testsSimon Pilgrim2016-07-021-0/+407
| | | | llvm-svn: 274448
* [X86][AVX512] Add support for 512-bit PSHUFB loweringSimon Pilgrim2016-07-021-15/+3
| | | | llvm-svn: 274444
* [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to ↵Simon Pilgrim2016-07-021-0/+156
| | | | | | generic IR llvm-svn: 274443
* [X86][AVX512] Autoupgrade the MOVDDUP/MOVSLDUP/MOVSHDUP intrinsicsSimon Pilgrim2016-07-024-204/+202
| | | | llvm-svn: 274439
* [X86][AVX512] Add support for lowering shuffles to MOVDDUP/MOVSLDUP/MOVSHDUPSimon Pilgrim2016-07-022-8/+4
| | | | llvm-svn: 274436
* [X86][AVX512] Add test cases that should lower to MOVSLDUP/MOVSHDUPSimon Pilgrim2016-07-021-1/+21
| | | | llvm-svn: 274435
* [X86][AVX512] Add fast-isel shuffle testsSimon Pilgrim2016-07-022-0/+737
| | | | | | Its not worth trying to write out tests for all the avx512f builtins yet, just adding tests for lowering of generic IR as we transition to it (shuffles mainly right now). llvm-svn: 274434
* [esan|cfrag] Add counters for struct array accessesQin Zhao2016-07-022-38/+56
| | | | | | | | | | | | | | | | | Summary: Adds one counter to the struct counter array for counting struct array accesses. Adds instrumentation to insert counter update for struct array accesses. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D21594 llvm-svn: 274420
* [PM] Port ConstantHoisting to the new Pass ManagerMichael Kuperstein2016-07-021-0/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D21945 llvm-svn: 274411
* [codeview] Set the Nested and Scoped ClassOptions based on the scope chainReid Kleckner2016-07-023-6/+12
| | | | | | These are set on both the declaration record and the definition record. llvm-svn: 274410
* TII: Fix inlineasm size counting comments as instsMatt Arsenault2016-07-011-0/+106
| | | | | | | The main problem was counting comments on their own line as instructions. llvm-svn: 274405
* [CodeView] Include the offset of nested membersDavid Majnemer2016-07-011-0/+61
| | | | | | | | | | | | | Given something like: struct S { int a; struct { int b; }; }; We would fail to give 'b' offset 4. Instead, we would give it the offset it has inside of it's struct. llvm-svn: 274400
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