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* [X86] AMD Znver2 (Rome) Scheduler enablementGanesh Gopalasubramanian2020-01-101-0/+11
| | | | | | | | | | | | The patch gives out the details of the znver2 scheduler model. There are few improvements with respect to execution units, latencies and throughput when compared with znver1. The tests that were present for znver1 for llvm-mca tool were replicated. The latencies, execution units, timeline and throughput information are updated for znver2. Reviewers: craig.topper, Simon Pilgrim Differential Revision: https://reviews.llvm.org/D66088
* [NFC][MCA][X86] Add baseline test coverage for AMD Barcelona (aka K10, fam10h)Roman Lebedev2019-06-151-33/+38
| | | | | | Looking into sched model for that CPU ... llvm-svn: 363497
* [NFC][MCA][BdVer2] Add bdver2 runline into register-file-statistics.s testRoman Lebedev2018-11-101-0/+11
| | | | | | | Missed this one by accident when adding the initial version in rL345463 / rL345462 llvm-svn: 346585
* [NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler modelRoman Lebedev2018-10-271-0/+1
| | | | | | | | | | | | Adding the baseline tests in a preparatory NFC commit, so that the actual commit shows the *diff*. Yes, i'm aware that a few of these codegen-based sched tests are testing wrong instructions, i will fix that afterwards. For https://reviews.llvm.org/D52779 llvm-svn: 345462
* [utils] Stricter checking from update_mca_test_checks.pyGreg Bedwell2018-09-281-27/+27
| | | | | | | | | | | | | | | | If any prefixes have been specified on the RUN lines that do not end up ever actually getting printed, raise an Error. This is either an indication that the run lines just need cleaning up, or that something is more fundamentally wrong with the test. Also raise an Error if there are any blocks which cannot be checked because they are not uniquely covered by a prefix. Fixed up a couple of tests where the extra checking flagged up issues. Differential Revision: https://reviews.llvm.org/D48276 llvm-svn: 343332
* [X86][Znver1] Specify Register Files, RCU; FP scheduler capacity.Roman Lebedev2018-06-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | Summary: First off: i do not have any access to that processor, so this is purely theoretical, no benchmarks. I have been looking into b**d**ver2 scheduling profile, and while cross-referencing the existing b**t**ver2, znver1 profiles, and the reference docs (`Software Optimization Guide for AMD Family {15,16,17}h Processors`), i have noticed that only b**t**ver2 scheduling profile specifies these. Also, there is no mca test coverage. Reviewers: RKSimon, craig.topper, courbet, GGanesh, andreadb Reviewed By: GGanesh Subscribers: gbedwell, vprasad, ddibyend, shivaram, Ashutosh, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D47676 llvm-svn: 335099
* [MCA] Add -summary-view optionRoman Lebedev2018-06-151-28/+0
| | | | | | | | | | | | | | | | | | | Summary: While that is indeed a quite interesting summary stat, there are cases where it does not really add anything other than consuming extra lines. Declutters the output of D48190. Reviewers: RKSimon, andreadb, courbet, craig.topper Reviewed By: andreadb Subscribers: javed.absar, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48209 llvm-svn: 334833
* [MCA][x86][NFC] Add tests for -register-file-stats, -scheduler-statsRoman Lebedev2018-06-151-0/+55
Summary: There does not seem to be any other tests for this. Split off from D47676. Reviewers: RKSimon, craig.topper, courbet, andreadb Reviewed By: andreadb Subscribers: javed.absar, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D48190 llvm-svn: 334832
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