summaryrefslogtreecommitdiffstats
path: root/llvm/test/tools/llvm-mca/X86/BtVer2/resources-sse41.s
Commit message (Collapse)AuthorAgeFilesLines
* [X86][Btver2] Fix BLENDV and AESDEC schedulesSimon Pilgrim2018-10-021-7/+7
| | | | | | Match AMD Fam16h SOG + llvm-exegesis tests llvm-svn: 343597
* [X86][BtVer2] Fix PHMINPOS schedule resources typoSimon Pilgrim2018-09-281-4/+4
| | | | | | PHMINPOS can run on either JFPU pipe llvm-svn: 343299
* [X86][Btver2] (V)MPSADBW instructions take 3uops not 1Simon Pilgrim2018-09-271-2/+2
| | | | llvm-svn: 343238
* [llvm-mca] Use a different character to flag instructions with side-effects ↵Andrea Di Biagio2018-07-111-1/+1
| | | | | | | | | | | | | | | | | | | | | in the Instruction Info View. NFC This makes easier to identify changes in the instruction info flags. It also helps spotting potential regressions similar to the one recently introduced at r336728. Using the same character to mark MayLoad/MayStore/HasSideEffects is problematic for llvm-lit. When pattern matching substrings, llvm-lit consumes tabs and spaces. A change in position of the flag marker may not trigger a test failure. This patch only changes the character used for flag `hasSideEffects`. The reason why I didn't touch other flags is because I want to avoid spamming the mailing because of the massive diff due to the numerous tests affected by this change. In future, each instruction flag should be associated with a different character in the Instruction Info View. llvm-svn: 336797
* [llvm-mca] Make sure not to end the test files with an empty line.Roman Lebedev2018-06-041-1/+0
| | | | | | | | | | | | | | | | | | | Summary: It's super irritating. [properly configured] git client then complains about that double-newline, and you have to use `--force` to ignore the warning, since even if you fix it manually, it will be reintroduced the very next runtime :/ Reviewers: RKSimon, andreadb, courbet, craig.topper, javed.absar, gbedwell Reviewed By: gbedwell Subscribers: javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47697 llvm-svn: 333887
* [X86][BtVer2] Improve simulation of (V)PINSR valuesSimon Pilgrim2018-05-181-6/+6
| | | | | | Include the 6cy delay transferring from the GPR to FPU. llvm-svn: 332737
* [llvm-mca] Regenerate tests after r332381 and r332361. NFCAndrea Di Biagio2018-05-161-208/+208
| | | | llvm-svn: 332447
* [X86] Add SchedWriteFRnd fp rounding scheduler classesSimon Pilgrim2018-05-041-9/+9
| | | | | | | | Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions. Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA. llvm-svn: 331515
* [X86] Split off PHMINPOSUW to their own schedule classSimon Pilgrim2018-04-241-3/+3
| | | | | | This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default. llvm-svn: 330756
* [UpdateTestChecks] Add update_mca_test_checks.py scriptGreg Bedwell2018-04-181-0/+112
| | | | | | | | | | | This script can be used to regenerate tests in the test/tools/llvm-mca directory (PR36904). Regenerated a number of tests using the pattern: test/tools/llvm-mca/*/*/*.s Differential Revision: https://reviews.llvm.org/D45369 llvm-svn: 330246
* [X86][Btver2] Add vector extract costsSimon Pilgrim2018-04-081-9/+9
| | | | llvm-svn: 329524
* [X86][Btver2] Strip unnecessary check prefixes from resources testsSimon Pilgrim2018-04-041-1/+1
| | | | llvm-svn: 329192
* [X86] Add SchedRW for PMULLDCraig Topper2018-03-311-2/+2
| | | | | | | | | | | | | | | | | | | Summary: It seems many CPUs don't implement this instruction as well as the other vector multiplies. Often using a multi uop flow. Silvermont in particular has a 7 uop flow with 11 cycle throughput. Sandy Bridge implements it as a single uop with 5 cycle latency and 1 cycle throughput. But Haswell and later use 2 uops with 10 cycle latency and 2 cycle throughput. This patch adds a new X86SchedWritePair we can use to tag this instruction separately. I've provided correct information for Silvermont, Btver2, and Sandy Bridge. I've removed the InstRWs for SandyBridge. I've left Haswell/Broadwell/Skylake InstRWs in place because I wasn't sure how to account for the different load latency between 128 and 256 bits. I also left Znver1 InstRWs in place because the existing values don't match Agner's spreadsheet. I also left a FIXME in the SandyBridge model because it being used for the "generic" model is too optimistic for the 256/512-bit versions since those are multiple uops on all known CPUs. Reviewers: RKSimon, GGanesh, courbet Reviewed By: RKSimon Subscribers: gchatelet, gbedwell, andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D44972 llvm-svn: 328914
* [X86][Btver2] Account for the "+i" integer pipe transfer costs (1cy use of ↵Simon Pilgrim2018-03-261-2/+2
| | | | | | JALU0 for GPR PRF write) llvm-svn: 328536
* [llvm-mca] Add flag -instruction-tables to print the theoretical resource ↵Andrea Di Biagio2018-03-261-75/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pressure distribution for instructions (PR36874) The goal of this patch is to address most of PR36874. To fully fix PR36874 we need to split the "InstructionInfo" view from the "SummaryView". That would make easy to check the latency and rthroughput as well. The patch reuses all the logic from ResourcePressureView to print out the "instruction tables". We have an entry for every instruction in the input sequence. Each entry reports the theoretical resource pressure distribution. Resource pressure is uniformly distributed across all the processor resource units of a group. At the moment, the backend pipeline is not configurable, so the only way to fix this is by creating a different driver that simply sends instruction events to the resource pressure view. That means, we don't use the Backend interface. Instead, it is simpler to just have a different code-path for when flag -instruction-tables is specified. Once Clement addresses bug 36663, then we can port the "instruction tables" logic into a stage of our configurable pipeline. Updated the BtVer2 test cases (thanks Simon for the help). Now we pass flag -instruction-tables to each modified test. Differential Revision: https://reviews.llvm.org/D44839 llvm-svn: 328487
* [X86][Btver2] Cleanup TEST instructions to use JFPA (+JFPX on ymms) function ↵Simon Pilgrim2018-03-231-2/+2
| | | | | | unit llvm-svn: 328343
* [X86][Btver2] Cleanup DPPS/DPPD instructions to use JFPA/JFPM function unitsSimon Pilgrim2018-03-231-69/+69
| | | | llvm-svn: 328324
* [X86][Btver2] Fix MicroOps counts for DPPS/YMM memory folded instructionsSimon Pilgrim2018-03-231-18/+18
| | | | | | This was due to a misunderstanding over what llvm calls a micro-op (retirement unit) is actually called a macro-op on the AMD/Jaguar target. Folded loads don't affect num macro ops. llvm-svn: 328320
* [X86][Btver2] Vector move/load/store instructions use a JFPU01 scheduler ↵Simon Pilgrim2018-03-231-64/+64
| | | | | | pipe and JFPX/JVALU function unit as well as the AGUs llvm-svn: 328304
* [X86] Match vpblendvb/vblendvps/vblendvpd itineraries to the SSE equivalent. ↵Craig Topper2018-03-231-66/+66
| | | | | | Change pblendvb/blendvps/blendvpd to use WriteFVarBlend llvm-svn: 328294
* [X86][Btver2] Correctly distinguish between scheduling pipe and functional ↵Simon Pilgrim2018-03-181-89/+89
| | | | | | | | | | unit for JWriteResFpuPair defs Jaguar's FPU has 2 scheduler pipes (JFPU0/JFPU1) which forward to multiple functional sub-units each. We need to model that an micro-op will both consume the scheduler pipe and a functional unit. This patch just handles the ops defined through JWriteResFpuPair, I'll go through the custom cases later. llvm-svn: 327791
* [X86][Btver2] Add llvm-mca tests to show pipe resource usage of most vector ↵Simon Pilgrim2018-03-181-0/+261
instructions Hopefully these tests can be easily reused should any other subtarget get in depth llvm-mca coverage (we can either copy the tests or move them into a common dir and run it with multiple prefixes). llvm-svn: 327788
OpenPOWER on IntegriCloud