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* [MCA] Fix test cases (NFC)Evandro Menezes2019-11-2210-30/+30
| | | | Fix the test cases for Exynos M5 that break under Darwin.
* [AArch64] Add the pipeline model for Exynos M5Evandro Menezes2019-11-2228-34/+2335
| | | | Add the scheduling and cost models for Exynos M5.
* Revert "[AArch64] Add the pipeline model for Exynos M5"Eric Christopher2019-11-2028-2335/+34
| | | | | | as it's causing test failures in llvm-mca. This reverts commit 9bdfee2a3bd13d405ce1592930182f23849d2897.
* [AArch64] Add the pipeline model for Exynos M5Evandro Menezes2019-11-2028-34/+2335
| | | | Add the scheduling and cost models for Exynos M5.
* [mca] Fix test case (NFC)Evandro Menezes2019-10-311-6/+6
| | | | Fix test case for Darwin builds.
* [AArch64] Update for ExynosEvandro Menezes2019-10-311-0/+71
| | | | Fix the costs of `add` and `orr` with an immediate operand.
* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-304-46/+0
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* [llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCIAndrea Di Biagio2019-04-081-1/+1
| | | | | | | | | It makes more sense to print out the number of micro opcodes that are issued every cycle rather than the number of instructions issued per cycle. This behavior is also consistent with the dispatch-stats: numbers from the two views can now be easily compared. llvm-svn: 357919
* [llvm-mca] Update tests for Exynos (NFC)Evandro Menezes2019-01-114-0/+46
| | | | | | Update test cases for Exynos M4. llvm-svn: 350961
* [llvm-mca] Update the Exynos test cases (NFC)Evandro Menezes2019-01-081-18/+18
| | | | | | Add more entropy to the test cases. llvm-svn: 350662
* [llvm-mca] Rename directory for the Cortex tests (NFC)Evandro Menezes2018-12-192-0/+0
| | | | llvm-svn: 349688
* [llvm-mca] Update Exynos test cases (NFC)Evandro Menezes2018-12-192-108/+0
| | | | llvm-svn: 349687
* [AArch64] Improve the Exynos M3 pipeline modelEvandro Menezes2018-12-191-1/+1
| | | | llvm-svn: 349652
* [llvm-mca] Split test (NFC)Evandro Menezes2018-12-192-29/+56
| | | | | | | Split the Exynos test of the register offset addressing mode into separate loads and stores tests. llvm-svn: 349651
* [llvm-mca] Improve test (NFC)Evandro Menezes2018-12-181-18/+56
| | | | | | Add more instruction variations for Exynos. llvm-svn: 349567
* [llvm-mca] Update the Exynos test cases (NFC)Evandro Menezes2018-12-185-49/+60
| | | | | | Add more entropy to the test cases. llvm-svn: 349537
* [AArch64] Refactor the Exynos scheduling predicatesEvandro Menezes2018-12-103-50/+47
| | | | | | | | | Refactor the scheduling predicates based on `MCInstPredicate`. In this case, for the Exynos processors. Differential revision: https://reviews.llvm.org/D55345 llvm-svn: 348774
* [llvm-mca] Add new tests for Exynos (NFC)Evandro Menezes2018-12-103-0/+150
| | | | llvm-svn: 348766
* Fix test/tools/llvm-mca/AArch64/Exynos/direct-branch.s on MacHans Wennborg2018-12-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | It was failing as below. Adding a triple seems to help. -- : 'RUN: at line 2';   /work/llvm.combined/build.release/bin/llvm-mca -march=aarch64 -mcpu=exynos-m1 -resource-pressure=false < /work/llvm.combined/llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s | /work/llvm.combined/build.release/bin/FileCheck /work/llvm.combined/llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s -check-prefixes=ALL,M1 : 'RUN: at line 3';   /work/llvm.combined/build.release/bin/llvm-mca -march=aarch64 -mcpu=exynos-m3 -resource-pressure=false < /work/llvm.combined/llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s | /work/llvm.combined/build.release/bin/FileCheck /work/llvm.combined/llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s -check-prefixes=ALL,M3 -- Exit Code: 1 Command Output (stderr): -- /work/llvm.combined/llvm/test/tools/llvm-mca/AArch64/Exynos/direct-branch.s:36:12: error: M1-NEXT: expected string not found in input            ^ <stdin>:21:2: note: scanning from here  1 0 0.25 b Ltmp0  ^ -- llvm-svn: 348577
* [llvm-mca] Improve test (NFC)Evandro Menezes2018-12-071-8/+14
| | | | | | Add more instructions to the test for Cortex. llvm-svn: 348565
* [llvm-mca] Improve test (NFC)Evandro Menezes2018-12-071-3/+4
| | | | | | Add a label to make explicit that the branch is short for Exynos. llvm-svn: 348564
* [llvm-mca] Simplify test (NFC)Evandro Menezes2018-12-051-27/+11
| | | | llvm-svn: 348395
* [llvm-mca] Sort test run lines (NFC)Evandro Menezes2018-12-051-1/+1
| | | | llvm-svn: 348393
* [AArch64] Refactor the scheduling predicates (2/3) (NFC)Evandro Menezes2018-11-261-5/+5
| | | | | | | | | Refactor the scheduling predicates based on `MCInstPredicate`. In this case, `AArch64InstrInfo::hasShiftedReg()`. Differential revision: https://reviews.llvm.org/D54820 llvm-svn: 347598
* [AArch64] Refactor the scheduling predicates (1/3) (NFC)Evandro Menezes2018-11-261-6/+6
| | | | | | | | | Refactor the scheduling predicates based on `MCInstPredicate`. In this case, `AArch64InstrInfo::isScaledAddr()` Differential revision: https://reviews.llvm.org/D54777 llvm-svn: 347597
* [TableGen] Emit more variant transitionsEvandro Menezes2018-11-232-8/+46
| | | | | | | | | | | | | | | | | | | | | | `llvm-mca` relies on the predicates to be based on `MCSchedPredicate` in order to resolve the scheduling for variant instructions. Otherwise, it aborts the building of the instruction model early. However, the scheduling model emitter in `TableGen` gives up too soon, unless all processors use only such predicates. In order to allow more processors to be used with `llvm-mca`, this patch emits scheduling transitions if any processor uses these predicates. The transition emitted for the processors using legacy predicates is the one specified with `NoSchedPred`, which is based on `MCSchedPredicate`. Preferably, `llvm-mca` should instead assume a reasonable default when a variant transition is not based on `MCSchedPredicate` for a given processor. This issue should be revisited in the future. Differential revision: https://reviews.llvm.org/D54648 llvm-svn: 347504
* [llvm-mca] Add test case (NFC)Evandro Menezes2018-11-221-0/+7
| | | | | | Add test case that will serve as the base for D54820. llvm-svn: 347440
* [llvm-mca] Add test case (NFC)Evandro Menezes2018-11-211-2/+2
| | | | | | Fix previous commit r347434. llvm-svn: 347437
* [llvm-mca] Add test case (NFC)Evandro Menezes2018-11-211-0/+9
| | | | | | Add test case that will serve as the base for D54777. llvm-svn: 347434
* [llvm-mca] Add fields "Total uOps" and "uOps Per Cycle" to the report ↵Andrea Di Biagio2018-08-295-11/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | generated by the SummaryView. This patch adds two new fields to the perf report generated by the SummaryView. Fields are now logically organized into two small groups; only the second group contains throughput indicators. Example: ``` Iterations: 100 Instructions: 300 Total Cycles: 414 Total uOps: 700 Dispatch Width: 4 uOps Per Cycle: 1.69 IPC: 0.72 Block RThroughput: 4.0 ``` This patch also updates the docs for llvm-mca. Due to the nature of this change, several tests in the tools/llvm-mca directory were affected, and had to be updated using script `update_mca_test_checks.py`. llvm-svn: 340946
* [llvm-mca] Fix PR38575: Avoid an invalid implicit truncation of a processor ↵Andrea Di Biagio2018-08-151-0/+82
| | | | | | | | | | | | | | | | | resource mask (an uint64_t value) to unsigned. This patch fixes a regression introduced at revision 338702. A processor resource mask was incorrectly implicitly truncated to an unsigned quantity. Later on, the truncated mask was used to initialize an element of a vector of processor resource descriptors. On targets with more than 32 processor resources, some elements of the vector are left uninitialized. As a consequence, this bug might have eventually caused a crash due to null dereference in the Scheduler. This patch fixes PR38575, and adds a test for it. llvm-svn: 339768
* [llvm-mca] Use a different character to flag instructions with side-effects ↵Andrea Di Biagio2018-07-113-3/+3
| | | | | | | | | | | | | | | | | | | | | in the Instruction Info View. NFC This makes easier to identify changes in the instruction info flags. It also helps spotting potential regressions similar to the one recently introduced at r336728. Using the same character to mark MayLoad/MayStore/HasSideEffects is problematic for llvm-lit. When pattern matching substrings, llvm-lit consumes tabs and spaces. A change in position of the flag marker may not trigger a test failure. This patch only changes the character used for flag `hasSideEffects`. The reason why I didn't touch other flags is because I want to avoid spamming the mailing because of the massive diff due to the numerous tests affected by this change. In future, each instruction flag should be associated with a different character in the Instruction Info View. llvm-svn: 336797
* [CodeGen] assume max/default throughput for unspecified instructionsSanjay Patel2018-06-051-1/+3
| | | | | | | | | | | | | This is a fix for the problem arising in D47374 (PR37678): https://bugs.llvm.org/show_bug.cgi?id=37678 We may not have throughput info because it's not specified in the model or it's not available with variant scheduling, so assume that those instructions can execute/complete at max-issue-width. Differential Revision: https://reviews.llvm.org/D47723 llvm-svn: 334055
* [llvm-mca] Make sure not to end the test files with an empty line.Roman Lebedev2018-06-044-4/+0
| | | | | | | | | | | | | | | | | | | Summary: It's super irritating. [properly configured] git client then complains about that double-newline, and you have to use `--force` to ignore the warning, since even if you fix it manually, it will be reintroduced the very next runtime :/ Reviewers: RKSimon, andreadb, courbet, craig.topper, javed.absar, gbedwell Reviewed By: gbedwell Subscribers: javed.absar, tschuett, gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47697 llvm-svn: 333887
* [UpdateTestChecks] Improved update_mca_test_checks block analysisGreg Bedwell2018-05-244-23/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously update_mca_test_checks worked entirely at "block" level where a block is some sequence of lines delimited by at least one empty line. This generally worked well, but could sometimes lead to excessive repetition of check lines for various prefixes if some block was almost identical between prefixes, but not quite (for example, due to a different dispatch width in the otherwise identical summary views). This new analyis attempts to split blocks further in the case where the following conditions are met: a) There is some prefix common to every RUN line (typically 'ALL'). b) The first line of the block is common to the output with every prefix. c) The block has the same number of lines for the output with every prefix. Also, regenerated all llvm-mca test files with the following command: update_mca_test_checks.py "../test/tools/llvm-mca/*/*.s" "../test/tools/llvm-mca/*/*/*.s" The new analysis showed a "multiple lines not disambiguated by prefixes" warning for test "AArch64/Exynos/scheduler-queue-usage.s" so I've also added some explicit prefixes to each of the RUN lines in that test. Differential Revision: https://reviews.llvm.org/D47321 llvm-svn: 333204
* [llvm-mca] Removed an empty line generated by the timeline view. NFC.Andrea Di Biagio2018-05-212-4/+2
| | | | | | Also, regenerate all tests. llvm-svn: 332853
* [llvm-mca] Regenerate tests after r332381 and r332361. NFCAndrea Di Biagio2018-05-163-39/+39
| | | | llvm-svn: 332447
* [llvm-mca] Correctly handle zero-latency stores that consume pipeline resources.Andrea Di Biagio2018-04-301-0/+44
| | | | | | | | | | | | | | | | This fixes PR37293. We can have scheduling classes with no write latency entries, that still consume processor resources. We don't want to treat those instructions as zero-latency instructions; they still have to be issued to the underlying pipelines, so they still consume resource cycles. This is likely to be a regression which I have accidentally introduced at revision 330807. Now, if an instruction has a non-empty set of write processor resources, we conservatively treat it as a normal (i.e. non zero-latency) instruction. llvm-svn: 331193
* [UpdateTestChecks] Add update_mca_test_checks.py scriptGreg Bedwell2018-04-183-28/+36
| | | | | | | | | | | This script can be used to regenerate tests in the test/tools/llvm-mca directory (PR36904). Regenerated a number of tests using the pattern: test/tools/llvm-mca/*/*/*.s Differential Revision: https://reviews.llvm.org/D45369 llvm-svn: 330246
* [llvm-mca] Move the logic that prints scheduler statistics from ↵Andrea Di Biagio2018-04-111-3/+9
| | | | | | | | BackendStatistics to its own view. Added flag -scheduler-stats to print scheduler related statistics. llvm-svn: 329792
* Reapply "[llvm-mca] Do not separate iterations with a newline in the ↵Andrea Di Biagio2018-04-103-13/+12
| | | | | | | | timeline view." This reapplies r329403 with a fix for the floating point rounding issue. llvm-svn: 329680
* Revert r329403 "[llvm-mca] Do not separate iterations with a newline in the ↵Hans Wennborg2018-04-093-12/+13
| | | | | | | | | | | | timeline view." This made AArch64/CortexA57/direct-branch.s fail on Windows, e.g. http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/11251 > Also, update a few tests to minimize the diff in D45369. > No functional change intended. llvm-svn: 329569
* [llvm-mca] Do not separate iterations with a newline in the timeline view.Andrea Di Biagio2018-04-063-13/+12
| | | | | | | Also, update a few tests to minimize the diff in D45369. No functional change intended. llvm-svn: 329403
* [llvm-mca] BackendStatistics: early exit from method printSchedulerUsage if theAndrea Di Biagio2018-03-101-0/+7
| | | | | | no scheduler resources were consumed. llvm-svn: 327215
* [llvm-mca] Fix handling of zero-latency instructions.Andrea Di Biagio2018-03-083-0/+100
This patch fixes a problem found when testing zero latency instructions on target AArch64 -mcpu=exynos-m3 / -mcpu=exynos-m1. On Exynos-m3/m1, direct branches are zero-latency instructions that don't consume any processor resources. The DispatchUnit marks zero-latency instructions as "executed", so that no scheduling is required. The event of instruction executed is then notified to all the listeners, and the reorder buffer (managed by the RetireControlUnit) is updated. In particular, the entry associated to the zero-latency instruction in the reorder buffer is marked as executed. Before this patch, the DispatchUnit forgot to assign a retire control unit token (RCUToken) to the zero-latency instruction. As a consequence, the RCUToken was used uninitialized. This was causing a crash in the RetireControlUnit logic. Fixes PR36650. llvm-svn: 327056
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