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* [InstCombine] reassociateShiftAmtsOfTwoSameDirectionShifts(): fix miscompile ↵Roman Lebedev2020-02-271-2/+5
| | | | | | | | | | | | | | | | | | | (PR44802) As input, we have the following pattern: Sh0 (Sh1 X, Q), K We want to rewrite that as: Sh x, (Q+K) iff (Q+K) u< bitwidth(x) While we know that originally (Q+K) would not overflow (because 2 * (N-1) u<= iN -1), we may have looked past extensions of shift amounts. so it may now overflow in smaller bitwidth. To ensure that does not happen, we need to ensure that the total maximal shift amount is still representable in that smaller bitwidth. If the overflow would happen, (Q+K) u< bitwidth(x) check would be bogus. https://bugs.llvm.org/show_bug.cgi?id=44802 (cherry picked from commit 781d077afb0ed9771c513d064c40170c1ccd21c9)
* [NFC][InstCombine] Add shift amount reassociation miscompile example from ↵Roman Lebedev2020-02-271-0/+15
| | | | | | | PR44802 https://bugs.llvm.org/show_bug.cgi?id=44802 (cherry picked from commit 425ef999385058143bb927aefe81daddcd43f623)
* [NFC][InstCombine] More test for "sign bit test via shifts" pattern (PR43595)Roman Lebedev2019-10-131-0/+116
| | | | | | | | | | | | | | | | While that pattern is indirectly handled via reassociateShiftAmtsOfTwoSameDirectionShifts(), that incursme one-use restriction on truncation, which is pointless since we know that we'll produce a single instruction. Additionally, *if* we are only looking for sign bit, we don't need shifts to be identical, which isn't the case in general, and is the blocker for me in bug in question: https://bugs.llvm.org/show_bug.cgi?id=43595 llvm-svn: 374726
* [InstCombine] Shift amount reassociation: fixup constantexpr handling (PR42484)Roman Lebedev2019-07-021-0/+15
| | | | | | | | | | | | | | | I was actually wondering if there was some nicer way than m_Value()+cast, but apparently what i was really "subconsciously" thinking about was correctness issue. hasNoUnsignedWrap()/hasNoUnsignedWrap() exist for Instruction, not for BinaryOperator, so let's just use m_Instruction(), thus both avoiding a cast, and a crash. Fixes https://bugs.llvm.org/show_bug.cgi?id=42484, https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=15587 llvm-svn: 364915
* [InstCombine] Shift amount reassociation (PR42391)Roman Lebedev2019-06-291-48/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Given pattern: `(x shiftopcode Q) shiftopcode K` we should rewrite it as `x shiftopcode (Q+K)` iff `(Q+K) u< bitwidth(x)` This is valid for any shift, but they must be identical. * https://rise4fun.com/Alive/9E2 * exact on both lshr => exact https://rise4fun.com/Alive/plHk * exact on both ashr => exact https://rise4fun.com/Alive/QDAA * nuw on both shl => nuw https://rise4fun.com/Alive/5Uk * nsw on both shl => nsw https://rise4fun.com/Alive/0plg Should fix [[ https://bugs.llvm.org/show_bug.cgi?id=42391 | PR42391]]. Reviewers: spatel, nikic, RKSimon Reviewed By: nikic Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63812 llvm-svn: 364712
* [NFC][InstCombine] Shift amount reassociation: revisit flag preservation testsRoman Lebedev2019-06-281-12/+26
| | | | llvm-svn: 364657
* [NFC][InstCombine] Shift amount reassociation: add flag preservation testRoman Lebedev2019-06-281-10/+55
| | | | | | | | | | | | | As discussed in https://reviews.llvm.org/D63812#inline-569870 * exact on both lshr => exact https://rise4fun.com/Alive/plHk * exact on both ashr => exact https://rise4fun.com/Alive/QDAA * nuw on both shl => nuw https://rise4fun.com/Alive/5Uk * nsw on both shl => nsw https://rise4fun.com/Alive/0plg So basically if the same flag is set on both original shifts -> set it on new shift. Don't think we can do anything with non-matching flags on shl. llvm-svn: 364652
* [NFC][InstCombine] Add shift amount reassociation tests (PR42391)Roman Lebedev2019-06-261-0/+167
https://bugs.llvm.org/show_bug.cgi?id=42391 https://rise4fun.com/Alive/9E2 llvm-svn: 364393
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