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* [NFC][InstCombine] More test for "sign bit test via shifts" pattern (PR43595)Roman Lebedev2019-10-131-3/+5
| | | | | | | | | | | | | | | | While that pattern is indirectly handled via reassociateShiftAmtsOfTwoSameDirectionShifts(), that incursme one-use restriction on truncation, which is pointless since we know that we'll produce a single instruction. Additionally, *if* we are only looking for sign bit, we don't need shifts to be identical, which isn't the case in general, and is the blocker for me in bug in question: https://bugs.llvm.org/show_bug.cgi?id=43595 llvm-svn: 374726
* [NFC][InstCombine] Tests for right-shift shift amount reassociation (w/ ↵Roman Lebedev2019-10-041-34/+0
| | | | | | | | trunc) (PR43564, PR42391) https://rise4fun.com/Alive/GEw llvm-svn: 373797
* [InstCombine] Recommit: Shift amount reassociation: shl-trunc-shl patternRoman Lebedev2019-08-071-44/+34
| | | | | | | | | | | | | | | | | This was initially committed in r368059 but got reverted in r368084 because there was a faulty logic in how the shift amounts type mismatch was being handled (it simply wasn't). I've added an explicit bailout before we SimplifyAddInst() - i don't think it's designed in general to handle differently-typed values, even though the actual problem only comes from ConstantExpr's. I have also changed the common type deduction, to not just blindly look past zext, but try to do that so that in the end types match. Differential Revision: https://reviews.llvm.org/D65380 llvm-svn: 368141
* Revert [InstCombine] Shift amount reassociation: shl-trunc-shl patternReid Kleckner2019-08-061-17/+44
| | | | | | | | | This reverts r368059 (git commit 0f957109761913c563922f1afd4ceb29ef21bbd0) This caused Clang to assert while self-hosting and compiling SystemZInstrInfo.cpp. Reduction is running. llvm-svn: 368084
* [InstCombine] Shift amount reassociation: shl-trunc-shl patternRoman Lebedev2019-08-061-44/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently `reassociateShiftAmtsOfTwoSameDirectionShifts()` only handles two shifts one after another. If the shifts are `shl`, we still can easily perform the fold, with no extra legality checks: https://rise4fun.com/Alive/OQbM If we have right-shift however, we won't be able to make it any simpler than it already is. After this the only thing missing here is constant-folding: (`NewShAmt >= bitwidth(X)`) * If it's a logical shift, then constant-fold to `0` (not `undef`) * If it's a `ashr`, then a splat of original signbit https://rise4fun.com/Alive/E1K https://rise4fun.com/Alive/i0V Reviewers: spatel, nikic, xbolva00 Reviewed By: spatel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65380 llvm-svn: 368059
* [NFC][InstCombine] Revisit tests in ↵Roman Lebedev2019-07-281-70/+35
| | | | | | shift-amount-reassociation-with-truncation-shl.ll llvm-svn: 367196
* [NFC][InstCombine] Shift amount reassociation: can have trunc between shl'sRoman Lebedev2019-07-281-0/+289
https://rise4fun.com/Alive/OQbM Not so simple for lshr/ashr, so those maybe later. https://bugs.llvm.org/show_bug.cgi?id=42391 llvm-svn: 367189
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