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path: root/llvm/test/Transforms/InstCombine/rem.ll
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* [InstCombine] Add support for vector srem->urem.Craig Topper2017-04-171-1/+1
* [InstCombine] Add missing testcases for srem->urem conversion. The vector ver...Craig Topper2017-04-171-0/+22
* [InstCombine] Support weird size element types in dyn_castNegVal.Craig Topper2017-04-111-4/+3
* [InstCombine] consolidate rem tests and update checks; NFCSanjay Patel2017-03-141-0/+143
* [InstCombine] regenerate checks; NFCSanjay Patel2017-03-141-177/+225
* [InstCombine] Move casts around shift operationsDavid Majnemer2017-01-041-5/+5
* [InstCombine] use m_APInt to allow icmp eq (srem X, C1), C2 folds for splat c...Sanjay Patel2016-08-031-4/+2
* add tests for icmp vector foldsSanjay Patel2016-07-221-0/+13
* Add safety check to InstCombiner::commonIRemTransformsSanjoy Das2016-06-051-0/+116
* Add test case for InstCombiner::commonIRemTransforms; NFCSanjoy Das2016-06-051-0/+23
* [ValueTracking, InstCombine] extend isKnownToBeAPowerOfTwo() to handle vector...Sanjay Patel2016-05-221-6/+2
* add tests for vector uremSanjay Patel2016-05-201-1/+23
* Add back commit r210029.Rafael Espindola2014-06-021-1/+1
* Revert "Add the nsw flag when we detect that an add will not signed overflow."Rafael Espindola2014-06-021-1/+1
* Add the nsw flag when we detect that an add will not signed overflow.Rafael Espindola2014-06-021-1/+1
* InstCombine: Teach most integer add/sub/mul/div combines how to deal with vec...Benjamin Kramer2014-01-191-0/+9
* isKnownToBeAPowerOfTwo: Strengthen isKnownToBeAPowerOfTwo's analysis on add i...David Majnemer2013-07-301-0/+32
* Update Transforms tests to use CHECK-LABEL for easier debugging. No functiona...Stephen Lin2013-07-141-18/+18
* Add a microoptimization for urem.Nick Lewycky2013-07-131-0/+9
* ValueTracking: Fix bugs in isKnownToBeAPowerOfTwoDavid Majnemer2013-07-091-15/+0
* ValueTracking: Teach isKnownToBeAPowerOfTwo about (ADD X, (XOR X, Y)) where X...David Majnemer2013-06-291-0/+15
* isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.David Majnemer2013-05-181-0/+14
* InstCombine: Flip the order of two urem transformsDavid Majnemer2013-05-121-0/+14
* InstCombine: Turn urem to bitwise-and more oftenDavid Majnemer2013-05-111-2/+51
* InstCombine: Add a missing irem identity (X % X -> 0).Benjamin Kramer2010-11-171-0/+5
* Use opt -S instead of piping bitcode output through llvm-dis.Dan Gohman2009-09-081-1/+1
* Change these tests to feed the assembly files to opt directly, insteadDan Gohman2009-09-081-1/+1
* Don't try to simplify urem and srem using arithmetic rules that don't workNick Lewycky2008-03-061-26/+33
* Remove llvm-upgrade and update test cases.Tanya Lattner2008-03-011-53/+50
* For PR1319:Reid Spencer2007-04-151-0/+1
* For PR1319:Reid Spencer2007-04-141-1/+0
* For PR411:Reid Spencer2007-01-301-1/+1
* Regression is gone, don't try to find it on clean target.Reid Spencer2007-01-171-0/+79
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