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* Revert "[HardwareLoops] Optimisation remarks"Sjoerd Meijer2019-10-161-7/+1
| | | | | | | | while I investigate the PPC build bot failures. This reverts commit ad763751565b9663bc338fa2ca5ade86c6ca22ec. llvm-svn: 374992
* [HardwareLoops] Optimisation remarksSjoerd Meijer2019-10-161-1/+7
| | | | | | | | | | | | This adds the initial plumbing to support optimisation remarks in the IR hardware-loop pass. I have left a todo in a comment where we can improve the reporting, and will iterate on that now that we have this initial support in. Differential Revision: https://reviews.llvm.org/D68579 llvm-svn: 374980
* [HardwareLoops] Loop counter guard intrinsicSam Parker2019-06-281-35/+40
| | | | | | | | | Introduce llvm.test.set.loop.iterations which sets the loop counter and also produces an i1 after testing that the count is not zero. Differential Revision: https://reviews.llvm.org/D63809 llvm-svn: 364628
* [CodeGen] Check for HardwareLoop Latch ExitBlockSam Parker2019-06-171-0/+46
The HardwareLoops pass finds exit blocks with a scevable exit count. If the target specifies to update the loop counter in a register, through a phi, we need to ensure that the exit block is a latch so that we can insert the phi with the correct value for the incoming edge. Differential Revision: https://reviews.llvm.org/D63336 llvm-svn: 363556
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