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* [AMDGPU] gfx908 targetStanislav Mekhanoshin2019-07-091-5/+22
| | | | | | Differential Revision: https://reviews.llvm.org/D64429 llvm-svn: 365525
* [AMDGPU] gfx1010 tests. NFC.Stanislav Mekhanoshin2019-05-131-1/+16
| | | | llvm-svn: 360615
* [llvm-readobj] Change -long-option to --long-option in tests. NFCFangrui Song2019-05-016-42/+42
| | | | | | | | | | We use both -long-option and --long-option in tests. Switch to --long-option for consistency. In the "llvm-readelf" mode, -long-option is discouraged as it conflicts with grouped short options and it is not accepted by GNU readelf. While updating the tests, change llvm-readobj -s to llvm-readobj -S to reduce confusion ("s" is --section-headers in llvm-readobj but --symbols in llvm-readelf). llvm-svn: 359649
* [yaml2obj][obj2yaml] - Change how symbol's binding is descibed when ↵George Rimar2019-04-031-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | parsing/dumping. Currently, YAML has the following syntax for describing the symbols: Symbols: Local: LocalSymbol1: ... LocalSymbol2: ... ... Global: GlobalSymbol1: ... Weak: ... GNUUnique: I.e. symbols are grouped by their bindings. That is not very convenient, because: It does not allow to set a custom binding, what can be useful for producing broken/special outputs for test cases. Adding a new binding would require to change a syntax (what we observed when added GNUUnique recently). It does not allow to change the order of the symbols in .symtab/.dynsym, i.e. currently all Local symbols are placed first, then Global, Weak and GNUUnique are following, but we are not able to change the order. It is not consistent. Binding is just one of the properties of the symbol, we do not group them by other properties. It makes the code more complex that it can be. This patch shows it can be simplified with the change performed. The patch changes the syntax to just: Symbols: Symbol1: ... Symbol2: ... ... With that, we are able to work with the binding field just like with any other symbol property. Differential revision: https://reviews.llvm.org/D60122 llvm-svn: 357595
* [yaml2obj]Allow explicit symbol indexes in relocations and emit error for ↵James Henderson2019-03-121-13/+0
| | | | | | | | | | | | | | | | | | | | | bad names Prior to this change, the "Symbol" field of a relocation would always be assumed to be a symbol name, and if no such symbol existed, the relocation would reference index 0. This confused me when I tried to use a literal symbol index in the field: since "0x1" was not a known symbol name, the symbol index was set as 0. This change falls back to treating unknown symbol names as integers, and emits an error if the name is not found and the string is not an integer. Note that the Symbol field is optional, so if a relocation doesn't reference a symbol, it shouldn't be specified. The new error required a number of test updates. Reviewed by: grimar, ruiu Differential Revision: https://reviews.llvm.org/D58510 llvm-svn: 355938
* AMDGPU: Enable code object v3 for AMDHSA onlyKonstantin Zhuravlyov2018-11-151-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D54186 llvm-svn: 346923
* AMDGPU: Add sram-ecc featureKonstantin Zhuravlyov2018-11-051-0/+61
| | | | | | Differential Revision: https://reviews.llvm.org/D53222 llvm-svn: 346177
* Revert r345542: AMDGPU: Enable code object v3 by defaultKonstantin Zhuravlyov2018-10-301-1/+1
| | | | | | It breaks mesa. llvm-svn: 345662
* AMDGPU: Enable code object v3 by defaultKonstantin Zhuravlyov2018-10-291-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D53525 llvm-svn: 345542
* [AMDGPU] Defined gfx909 Raven Ridge 2Tim Renouf2018-10-241-0/+16
| | | | | | | Differential Revision: https://reviews.llvm.org/D53418 Change-Id: Ie3d054f2e956c2768988c0f4c0ffd29a47294eef llvm-svn: 345120
* AMDGPU: Add Vega12 and Vega20Matt Arsenault2018-04-301-0/+33
| | | | | | | | Changes by Matt Arsenault Konstantin Zhuravlyov llvm-svn: 331215
* AMDGPU: Bring elf flags in sync with the specKonstantin Zhuravlyov2018-02-167-136/+555
| | | | | | | | | | | - Add MACH flags - Add XNACK flag - Add reserved flags - Minor cleanups in docs Differential Revision: https://reviews.llvm.org/D43356 llvm-svn: 325399
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer ↵Dmitry Preobrazhensky2017-11-201-4/+4
| | | | | | | | | | | | v_{add/addc/sub/subrev/subb/subbrev} See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765 Reviewers: tamazov, SamWot, arsenm, vpykhtin Differential Revision: https://reviews.llvm.org/D40088 llvm-svn: 318675
* Add base relative relocation record that can be used for the following case ↵Tony Tye2017-10-161-0/+4
| | | | | | | | | | | | | | (OpenCL example): static __global int Var = 0; __global int* Ptr[] = {&Var}; ... In this case Var is a non premptable symbol and so its address can be used as the value of Ptr, with a base relative relocation that will add the delta between the ELF address and the actual load address. Such relocations do not require a symbol. Differential Revision: https://reviews.llvm.org/D38909 llvm-svn: 315935
* AMDGPU: Add and set AMDGPU-specific e_flagsKonstantin Zhuravlyov2017-10-054-33/+106
| | | | | | Differential Revision: https://reviews.llvm.org/D38556 llvm-svn: 314987
* AMDGPU: Add ELFOSABI_AMDGPU_MESA3DKonstantin Zhuravlyov2017-10-031-0/+21
| | | | | | Differential Revision: https://reviews.llvm.org/D38387 llvm-svn: 314846
* AMDGPU: Add ELFOSABI_AMDGPU_PALKonstantin Zhuravlyov2017-10-033-2/+23
| | | | llvm-svn: 314843
* AMDGPU: Remove deprecated and unused elf definitionsKonstantin Zhuravlyov2017-06-051-15/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D33689 llvm-svn: 304737
* [AMDGPU] Fix typo in test filename. NFC.Konstantin Zhuravlyov2017-03-311-0/+0
| | | | llvm-svn: 299271
* [Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocationsKonstantin Zhuravlyov2016-10-141-20/+40
| | | | | | | | | | | | | | Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
* [AMDGPU] llvm-objdump: Skip amd_kernel_code_t only at the begining of kernel ↵Sam Kolton2016-08-171-0/+8
| | | | | | | | | | | | | | symbol. Summary: This change fix bug in AMDGPU disassembly. Previously, presence of symbols other than kernel symbols caused objdump to skip begining of those symbols. Reviewers: tstellarAMD, vpykhtin, Bigcheese, ruiu Subscribers: kzhuravl, arsenm Differential Revision: http://reviews.llvm.org/D21966 llvm-svn: 278921
* [yaml2obj] Missed updating a few test cases in r273915Chris Bieneman2016-06-271-1/+1
| | | | | | This should fix the broken bots. llvm-svn: 273918
* [yaml2obj] Remove --format option in favor of YAML tagsChris Bieneman2016-06-274-6/+7
| | | | | | | | | | | | | | | | | | | | | | Summary: Our YAML library's handling of tags isn't perfect, but it is good enough to get rid of the need for the --format argument to yaml2obj. This patch does exactly that. Instead of requiring --format, it infers the format based on the tags found in the object file. The supported tags are: !ELF !COFF !mach-o !fat-mach-o I have a corresponding patch that is quite large that fixes up all the in-tree test cases. Reviewers: rafael, Bigcheese, compnerd, silvas Subscribers: compnerd, llvm-commits Differential Revision: http://reviews.llvm.org/D21711 llvm-svn: 273915
* Support/ELF: Add AMDGPU relocation definitions to match documentationTom Stellard2016-06-171-0/+65
| | | | | | | | | | Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
* AMDGPU/SI: Add support for AMD code object version 2.Tom Stellard2016-05-051-1/+1
| | | | | | | | | | | | | | Summary: Version 2 is now the default. If you want to emit version 1, use the amdgcn--amdhsa-amdcov1 triple. Reviewers: arsenm, kzhuravl Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19283 llvm-svn: 268647
* [AMDGPU] llvm-objdump: Minimal HSA Code Object disassembler support.Valery Pykhtin2016-04-072-0/+77
| | | | | | | | | | | | Reenable reverted r265550 with endianness issue fixed. Variables of endian-aware types such as ulittle32_t should be explicitly casted to their natural equivalent types before passing it as vararg to printf like functions (format in my case). Added lit config file depending on AMDGPU target as the testcase uses assembler. Differential revision: http://reviews.llvm.org/D16998 llvm-svn: 265645
* Revert "[AMDGPU] llvm-objdump: Minimal HSA Code Object disassembler support."Valery Pykhtin2016-04-061-75/+0
| | | | | | This reverts commit r265550. There're problems with endianness on dumping instruction bytes. Need to find out how to use support::ulittle32_t type properly. llvm-svn: 265554
* [AMDGPU] llvm-objdump: Minimal HSA Code Object disassembler support.Valery Pykhtin2016-04-061-0/+75
| | | | | | Differential revision: http://reviews.llvm.org/D16998 llvm-svn: 265550
* [AMDGPU] add AMDGPU target support to ELFObjectFile.h headerValery Pykhtin2016-03-093-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D17144 llvm-svn: 263026
* ELFYAML: Add support for parsing AMDGPU section attribute flagsTom Stellard2015-11-131-1/+16
| | | | | | | | | | Reviewers: silvas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14444 llvm-svn: 253052
* ELFYAML: Enable parsing of EM_AMDGPUTom Stellard2015-07-311-0/+12
Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11263 llvm-svn: 243724
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