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* [WebAssembly] MC: Fix for address taken aliasesSam Clegg2017-12-221-28/+118
| | | | | | | | | | | | | | Previously, taking the address for an alias would result in: "Symbol not found in table index space" Increase test coverage for weak aliases. This code should be more efficient too as it avoids building the `IsAddressTaken` set. Differential Revision: https://reviews.llvm.org/D41510 llvm-svn: 321384
* [AMDGPU][MC] Corrected handling of negative expressionsDmitry Preobrazhensky2017-12-222-3/+11
| | | | | | | | | | See bug 35716: https://bugs.llvm.org/show_bug.cgi?id=35716 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41488 llvm-svn: 321372
* [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32Dmitry Preobrazhensky2017-12-222-0/+7
| | | | | | | | | | See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41186 llvm-svn: 321367
* [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky2017-12-223-0/+90
| | | | | | | | | | | | See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561 This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic. Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41437 llvm-svn: 321359
* [X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling ↵Craig Topper2017-12-222-0/+5
| | | | | | | | | | | | | | for prefetch instructions. Previously prefetch was only considered legal if sse was enabled, but it should be supported with 3dnow as well. The prfchw flag now imply at least some form of prefetch without the write hint is available, either the sse or 3dnow version. This is true even if 3dnow and sse are explicitly disabled. Similarly prefetchwt1 feature implies availability of prefetchw and the the prefetcht0/1/2/nta instructions. This way we can support _MM_HINT_ET0 using prefetchw and _MM_HINT_ET1 with prefetchwt1. And its assumed that if we have levels for the write hint we would have levels for the non-write hint, thus why we enable the sse prefetch instructions. I believe this behavior is consistent with gcc. I've updated the prefetch.ll to test all of these combinations. llvm-svn: 321335
* [mips] Fix the invalid EVA testSimon Dardis2017-12-211-23/+24
| | | | | | | | During the review of D40362 I spotted that this test wasn't actually testing the eva instructions due to '-mattr==eva', rather than '-mattr=+eva', which resulted in test having no effect. llvm-svn: 321273
* [ARM] Armv8-R DFB instructionSam Parker2017-12-214-0/+28
| | | | | | | | Implement MC support for the Armv8-R 'Data Full Barrier' instruction. Differential Revision: https://reviews.llvm.org/D41430 llvm-svn: 321256
* [WebAssembly] Fix local references to weak aliasesSam Clegg2017-12-211-18/+39
| | | | | | | | | | | | | | | | When weak aliases are used with in same translation unit we need to be able to directly reference to alias and not just the thing it is aliases. We do this by defining both a wasm import and a wasm export in this case that result in a single Symbol. This change is a partial revert of rL314245. A corresponding lld change address the previous issues we had with this. See: https://github.com/WebAssembly/tool-conventions/issues/34 Differential Revision: https://reviews.llvm.org/D41472 llvm-svn: 321242
* [AMDGPU, AsmParser] Enable the mnemonic spell corrector.Matt Arsenault2017-12-202-5/+55
| | | | | | Patch by Dmitry Venikov llvm-svn: 321202
* [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2Sander de Smalen2017-12-2037-223/+542
| | | | | | | | | | | This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of of r320992, r320986, r320973, and r320970 by reverting https://reviews.llvm.org/rL321024. The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158, so this patch-series should be safe to resubmit. llvm-svn: 321163
* [AArch64] Asm: Fix parsing of register aliases that have a name starting ↵Sander de Smalen2017-12-202-0/+11
| | | | | | | | | | | | | | | | with 'z' Summary: This fixes an issue as identified by @rnk in https://reviews.llvm.org/rL321029. Reviewers: rnk, fhahn, rengolin, efriedma, echristo, olista01 Reviewed By: rnk, fhahn Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, rnk Differential Revision: https://reviews.llvm.org/D41382 llvm-svn: 321158
* [AArch64] CCSIDR2 system registerSam Parker2017-12-203-0/+10
| | | | | | | | | | Implement the 'Current Cache Size' register that has been introduced as part of the Armv8.3 architecture. I originally missed this, and (hopefully) should be the final patch for assembler support. Differential Revision: https://reviews.llvm.org/D41396 llvm-svn: 321155
* [X86][CLFLUSH]: Adding full coverage of MC encoding for the CLFLUSH isa ↵Gadi Haber2017-12-204-0/+104
| | | | | | | | | | | | | | sets.<NFC> NFC. Adding MC regressions tests to cover the CLFLSH and CLFLUSHOPT isa sets. This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, craig.topper, m_zuckerman Differential Revision: https://reviews.llvm.org/D41331 Change-Id: Ifa643dd52f1b7184c52bc1806038dc74b234fc65 llvm-svn: 321153
* Add test for .req directive starting with 'p'Reid Kleckner2017-12-181-0/+5
| | | | | | Reduced test case from libjpeg_turbo. llvm-svn: 321029
* [X86] Don't use NOPL when the assembler is passed an empty CPU string. ↵Craig Topper2017-12-1812-23/+23
| | | | | | | | | | Update tests to force a CPU with NOPL Empty string should be equivalent to "generic" which doesn't allow NOPL. Force tests to use specificy 'pentiumpro' to guarantee NOPL. Fixes PR35686 llvm-svn: 321026
* Revert "[AArch64][SVE] Asm" changes, they broke libjpeg_turboReid Kleckner2017-12-1837-548/+223
| | | | | | | | | | This reverts changes r320992, r320986, r320973, and r320970. r320970 by itself breaks the test case, and the rest depend on it. Test case will land soon. llvm-svn: 321024
* [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specifiedSander de Smalen2017-12-186-69/+69
| | | | | | | | | | | | | | Summary: Patch [4/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch further improves diagnostic messages for when the SVE feature is not specified. Reviewers: rengolin, fhahn, olista01, echristo, efriedma Reviewed By: fhahn Subscribers: sdardis, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D40363 llvm-svn: 320992
* [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled ↵Sander de Smalen2017-12-1829-218/+220
| | | | | | | | | | | | | | | | | | | | | | | instruction Summary: When emitting a diagnostic for an invalid operand, a specific diagnostic should only be reported when the instruction being matched is actually enabled by the feature flags. Patch [3/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when the SVE feature is not specified. Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund Reviewed By: olista01, sdardis Subscribers: fhahn, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40362 llvm-svn: 320986
* [AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)Sander de Smalen2017-12-184-0/+294
| | | | | | | | | | | | | | Summary: Patch [2/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40361 llvm-svn: 320973
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-12-182-0/+29
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 320970
* AArch64: work around how Cyclone handles "movi.2d vD, #0".Tim Northover2017-12-181-0/+9
| | | | | | | | | | | For Cylone, the instruction "movi.2d vD, #0" is executed incorrectly in some rare circumstances. Work around the issue conservatively by avoiding the instruction entirely. This patch changes CodeGen so that problematic instructions are never generated, and the AsmParser so that an equivalent instruction is used (with a warning). llvm-svn: 320965
* [PowerPC, AsmParser] Enable the mnemonic spell correctorHal Finkel2017-12-161-0/+44
| | | | | | | | | | | r307148 added an assembly mnemonic spelling correction support and enabled it on ARM. This enables that support on PowerPC as well. Patch by Dmitry Venikov, thanks! Differential Revision: https://reviews.llvm.org/D40552 llvm-svn: 320911
* [X86] Fix XSAVE64 and similar instructions to not be allowed by the ↵Craig Topper2017-12-151-8/+0
| | | | | | | | | | assembler in 32-bit mode. There was a top level "let Predicates =" in the .td file that was overriding the Requires on each instruction. I've added an assert to the code emitter to catch more cases like this. I'm sure this isn't the only place where the right predicates aren't being applied. This assert already found that we don't block btq/btsq/btrq in 32-bit mode. llvm-svn: 320830
* [RISCV] Change shift amount operand of RVC shift instructions to ↵Alex Bradbury2017-12-153-1/+16
| | | | | | | | | | | | | | uimmlog2xlennonzero c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C. This patch adds uimmlog2xlennonzero to reflect this constraint as well as tests. Differential Revision: https://reviews.llvm.org/D41216 Patch by Shiva Chen. llvm-svn: 320799
* [RISCV] Enable emission of alias instructions by defaultAlex Bradbury2017-12-1527-134/+304
| | | | | | | | | | | | | | | | | | This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
* [WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtorsSam Clegg2017-12-151-39/+112
| | | | | | | | | | | | | | | Summary: - lowers @llvm.global_dtors by adding @llvm.global_ctors functions which register the destructors with `__cxa_atexit`. - impements @llvm.global_ctors with wasm start functions and linker metadata See [here](https://github.com/WebAssembly/tool-conventions/issues/25) for more background. Subscribers: jfb, dschuff, mgorny, jgravelle-google, aheejin, sunfish Differential Revision: https://reviews.llvm.org/D41211 llvm-svn: 320774
* [MC] Allow .file directives to be out-of-orderPaul Robinson2017-12-141-10/+10
| | | | llvm-svn: 320727
* [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa ↵Gadi Haber2017-12-144-0/+40436
| | | | | | | | | | | | | | | set.<NFC> NFC. Adding MC regressions tests to cover the AVX and AVX2 ISA sets. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. See revision: https://reviews.llvm.org/D39952 Reviewers: zvi, RKSimon, aymanmus, m_zuckerman Differential Revison: https://reviews.llvm.org/D40287 Change-Id: I304687a2b7abb473f79de99c31fc55c97b2662da llvm-svn: 320716
* Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.Sander de Smalen2017-12-142-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand. This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate. (Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win builder does not seem to rebuild AArch64GenAsmMatcher.inc with the newly built TableGen due to a missing dependency somewhere (see: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html)) Reviewers: craig.topper, olista01, rengolin, stoklund Reviewed By: olista01 Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40011 llvm-svn: 320711
* [X86][AES]: Adding full coverage of MC encoding for the AES and AVXAES isa ↵Gadi Haber2017-12-144-0/+1016
| | | | | | | | | | | | | | | sets.<NFC> NFC. Adding MC regressions tests to cover the AES and AVXAES ISA sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, m_zuckerman, RKSimon Differential Revision: https://reviews.llvm.org/D41154 Change-Id: I2564f9797628d0c070c4766f837f399337fb87d2 llvm-svn: 320670
* MC/AsmPrinter: Reduce code duplication.Matthias Braun2017-12-141-1/+1
| | | | | | | | | | Factor out duplicated code emitting mach-o version-min specifiers. This should be NFC but happens to fix a bug where the code in MCMachoStreamer didn't take the version skew between darwin and macos versions into account. llvm-svn: 320666
* MC: Add support for mach-o build_versionMatthias Braun2017-12-145-23/+108
| | | | | | | | LC_BUILD_VERSION is a new load command superseding the previously used LC_XXX_MIN_VERSION commands. This adds an assembler directive along with encoding/streaming support. llvm-svn: 320661
* [WebAssembly] Use bitfield types in wasm YAML representationSam Clegg2017-12-138-27/+27
| | | | | | Differential Revision: https://reviews.llvm.org/D41202 llvm-svn: 320642
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-131-0/+39
| | | | | | | | | | | | | | | | | | | | | Stores failed to decode at all since they didn't have a DecoderNamespace set. Loads worked, but did not change the register width displayed to match the numbmer of enabled channels. The number of printed registers for vaddr is still wrong, but I don't think that's encoded in the instruction so there's not much we can do about that. Image atomics are still broken. MIMG is the same encoding for SI/VI, but the image atomic classes are split up into encoding specific versions unlike every other MIMG instruction. They have isAsmParserOnly set on them for some reason. dmask is also special for these, so we probably should not have it as an explicit operand as it is now. llvm-svn: 320614
* [RISCV] Define sfence.vma InstAliases to match the GNU RISC-V toolsAlex Bradbury2017-12-132-1/+8
| | | | | | | | Unfortunately these aren't defined explicitly in the privileged spec, but the GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the usual `sfence.vma rs, rt`. llvm-svn: 320575
* [RISCV] Implement floating point assembler pseudo instructionsAlex Bradbury2017-12-132-0/+110
| | | | | | | | | | | | | | | Adds the assembler aliases for the floating point instructions which can be mapped to a single canonical instruction. The missing pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. This patch builds upon D40902. Differential Revision: https://reviews.llvm.org/D41071 Patch by Mario Werner. llvm-svn: 320569
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-139-3/+191
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
* [X86][BMI]: Adding full coverage of MC encoding for the BMI isa set.<NFC>Gadi Haber2017-12-134-0/+1104
| | | | | | | | | | | | | NFC. Adding MC regressions tests to cover the BMI1 and BMI2 ISA sets both 32 and 64 bit. This patch is part of a larger task to cover MC encoding of all X86 ISA Sets. started in revision: https://reviews.llvm.org/D39952 Reviewers: zvi, craig.topper, m_zuckerman, RKSimon Differential Revision: https://reviews.llvm.org/D41106 Change-Id: I033ce137b5b82d36e1e601cd5e0534637b43a4a9 llvm-svn: 320557
* [RISCV] Implement assembler pseudo instructions for RV32I and RV64IAlex Bradbury2017-12-125-0/+192
| | | | | | | | | | | | | | | | | | | | Adds the assembler pseudo instructions of RV32I and RV64I which can be mapped to a single canonical instruction. The missing pseudo instructions (e.g., call, tail, ...) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. Currently, alias emission is disabled by default to keep the patch minimal. Alias emission by default will be enabled in a subsequent patch which also updates all affected tests. Note that this patch should actually break the floating point MC tests. However, the used FileCheck configuration is not tight enought to detect the breakage. Differential Revision: https://reviews.llvm.org/D40902 Patch by Mario Werner. llvm-svn: 320487
* [RISCV] MC layer support for the instructions added in the privileged specAlex Bradbury2017-12-122-0/+39
| | | | | | | | | | | | | | | Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. llvm-svn: 320484
* Reland "[WebAssembly] Import the linear memory and function table."Sam Clegg2017-12-118-32/+39
| | | | | | Original change: https://reviews.llvm.org/D40875 llvm-svn: 320432
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-118-21/+250
| | | | llvm-svn: 320404
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-116-8/+232
| | | | | | | | | | | | See bugs 35494 and 35559: https://bugs.llvm.org/show_bug.cgi?id=35494 https://bugs.llvm.org/show_bug.cgi?id=35559 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41007 llvm-svn: 320375
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-117-1193/+16
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [AVR] Implement some missing code pathsDylan McKay2017-12-112-11/+35
| | | | | | This has been broken since r320009. llvm-svn: 320348
* PowerPC: support external pid instructions in MC layer.Tim Northover2017-12-102-0/+68
| | | | | | | | | | | This adds assembly & disassembly support for the e500mc "external pid" instructions. See https://reviews.llvm.org/D39249. Patch by vit9696 <vit9696@avp.su> llvm-svn: 320287
* Revert and accidentally committed revert commitDylan McKay2017-12-091-0/+61
| | | | | | This reverts commit r320245. llvm-svn: 320247
* Revert "[AVR] Override ParseDirective"Dylan McKay2017-12-091-61/+0
| | | | | | This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418. llvm-svn: 320245
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-0812-20/+16
| | | | | | | | | | | | - Add gfx704 - Change bonaire to gfx704 - Remove gfx804 - Remove gfx901 - Remove gfx903 Differential Revision: https://reviews.llvm.org/D40046 llvm-svn: 320194
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-074-2/+62
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40002 Patch by Shiva Chen. llvm-svn: 320038
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