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| author | Sander de Smalen <sander.desmalen@arm.com> | 2017-12-20 11:02:42 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2017-12-20 11:02:42 +0000 |
| commit | cd6be960cead10b9d8c68686487f92418232c1a5 (patch) | |
| tree | 2fa4b7e6c2644e8909e9b327e275afa72f2536d0 /llvm/test/MC | |
| parent | 6db5d027c649666e3b1ce02db914d6152833830d (diff) | |
| download | bcm5719-llvm-cd6be960cead10b9d8c68686487f92418232c1a5.tar.gz bcm5719-llvm-cd6be960cead10b9d8c68686487f92418232c1a5.zip | |
[AArch64][SVE] Re-submit patch series for ZIP1/ZIP2
This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of
of r320992, r320986, r320973, and r320970 by reverting
https://reviews.llvm.org/rL321024.
The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158,
so this patch-series should be safe to resubmit.
llvm-svn: 321163
Diffstat (limited to 'llvm/test/MC')
37 files changed, 542 insertions, 223 deletions
diff --git a/llvm/test/MC/AArch64/SVE/add.s b/llvm/test/MC/AArch64/SVE/add.s index 30cb6ffc305..fa073ce1107 100644 --- a/llvm/test/MC/AArch64/SVE/add.s +++ b/llvm/test/MC/AArch64/SVE/add.s @@ -10,95 +10,95 @@ add z31.s, z31.s, z31.s // CHECK-INST: add z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x03,0xbf,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 03 bf 04 <unknown> add z23.d, z13.d, z8.d // CHECK-INST: add z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x01,0xe8,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: b7 01 e8 04 <unknown> add z0.s, z0.s, z0.s // CHECK-INST: add z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x00,0xa0,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 00 a0 04 <unknown> add z31.d, z31.d, z31.d // CHECK-INST: add z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x03,0xff,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 03 ff 04 <unknown> add z21.b, z10.b, z21.b // CHECK-INST: add z21.b, z10.b, z21.b // CHECK-ENCODING: [0x55,0x01,0x35,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 01 35 04 <unknown> add z31.b, z31.b, z31.b // CHECK-INST: add z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x03,0x3f,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 03 3f 04 <unknown> add z0.h, z0.h, z0.h // CHECK-INST: add z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x00,0x60,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 00 60 04 <unknown> add z23.b, z13.b, z8.b // CHECK-INST: add z23.b, z13.b, z8.b // CHECK-ENCODING: [0xb7,0x01,0x28,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: b7 01 28 04 <unknown> add z0.d, z0.d, z0.d // CHECK-INST: add z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x00,0xe0,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 00 e0 04 <unknown> add z31.h, z31.h, z31.h // CHECK-INST: add z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x03,0x7f,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 03 7f 04 <unknown> add z0.b, z0.b, z0.b // CHECK-INST: add z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x00,0x20,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 00 20 04 <unknown> add z21.d, z10.d, z21.d // CHECK-INST: add z21.d, z10.d, z21.d // CHECK-ENCODING: [0x55,0x01,0xf5,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 01 f5 04 <unknown> add z21.h, z10.h, z21.h // CHECK-INST: add z21.h, z10.h, z21.h // CHECK-ENCODING: [0x55,0x01,0x75,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 01 75 04 <unknown> add z21.s, z10.s, z21.s // CHECK-INST: add z21.s, z10.s, z21.s // CHECK-ENCODING: [0x55,0x01,0xb5,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 01 b5 04 <unknown> add z23.h, z13.h, z8.h // CHECK-INST: add z23.h, z13.h, z8.h // CHECK-ENCODING: [0xb7,0x01,0x68,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: b7 01 68 04 <unknown> add z23.s, z13.s, z8.s // CHECK-INST: add z23.s, z13.s, z8.s // CHECK-ENCODING: [0xb7,0x01,0xa8,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: b7 01 a8 04 <unknown> diff --git a/llvm/test/MC/AArch64/SVE/dot-req-diagnostics.s b/llvm/test/MC/AArch64/SVE/dot-req-diagnostics.s new file mode 100644 index 00000000000..c6626940907 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/dot-req-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+sve < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ERROR %s + +foo: +// CHECK: error: sve predicate register without type specifier expected + pbarb .req p1.b +// CHECK: error: sve predicate register without type specifier expected + pbarh .req p1.h +// CHECK: error: sve predicate register without type specifier expected + pbars .req p1.s +// CHECK: error: sve predicate register without type specifier expected + pbard .req p1.d + +// CHECK: error: sve vector register without type specifier expected + zbarb .req z1.b +// CHECK: error: sve vector register without type specifier expected + zbarh .req z1.h +// CHECK: error: sve vector register without type specifier expected + zbars .req z1.s +// CHECK: error: sve vector register without type specifier expected + zbard .req z1.d diff --git a/llvm/test/MC/AArch64/SVE/dot-req.s b/llvm/test/MC/AArch64/SVE/dot-req.s index c6816ea98b2..9bec12a6e61 100644 --- a/llvm/test/MC/AArch64/SVE/dot-req.s +++ b/llvm/test/MC/AArch64/SVE/dot-req.s @@ -1,6 +1,9 @@ // RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sve -show-encoding < %s 2>&1 | FileCheck %s foo: +// CHECK-NOT: error: + pbar .req p1 + // CHECK: add z0.s, z1.s, z2.s zbar .req z1 add z0.s, zbar.s, z2.s diff --git a/llvm/test/MC/AArch64/SVE/sub.s b/llvm/test/MC/AArch64/SVE/sub.s index 73a75ab859e..0dd83c1bc40 100644 --- a/llvm/test/MC/AArch64/SVE/sub.s +++ b/llvm/test/MC/AArch64/SVE/sub.s @@ -10,95 +10,95 @@ sub z0.h, z0.h, z0.h // CHECK-INST: sub z0.h, z0.h, z0.h // CHECK-ENCODING: [0x00,0x04,0x60,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 04 60 04 <unknown> sub z21.b, z10.b, z21.b // CHECK-INST: sub z21.b, z10.b, z21.b // CHECK-ENCODING: [0x55,0x05,0x35,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 05 35 04 <unknown> sub z31.h, z31.h, z31.h // CHECK-INST: sub z31.h, z31.h, z31.h // CHECK-ENCODING: [0xff,0x07,0x7f,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 07 7f 04 <unknown> sub z21.h, z10.h, z21.h // CHECK-INST: sub z21.h, z10.h, z21.h // CHECK-ENCODING: [0x55,0x05,0x75,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 05 75 04 <unknown> sub z31.b, z31.b, z31.b // CHECK-INST: sub z31.b, z31.b, z31.b // CHECK-ENCODING: [0xff,0x07,0x3f,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 07 3f 04 <unknown> sub z0.s, z0.s, z0.s // CHECK-INST: sub z0.s, z0.s, z0.s // CHECK-ENCODING: [0x00,0x04,0xa0,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 04 a0 04 <unknown> sub z23.b, z13.b, z8.b // CHECK-INST: sub z23.b, z13.b, z8.b // CHECK-ENCODING: [0xb7,0x05,0x28,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: b7 05 28 04 <unknown> sub z21.d, z10.d, z21.d // CHECK-INST: sub z21.d, z10.d, z21.d // CHECK-ENCODING: [0x55,0x05,0xf5,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 05 f5 04 <unknown> sub z21.s, z10.s, z21.s // CHECK-INST: sub z21.s, z10.s, z21.s // CHECK-ENCODING: [0x55,0x05,0xb5,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 55 05 b5 04 <unknown> sub z0.b, z0.b, z0.b // CHECK-INST: sub z0.b, z0.b, z0.b // CHECK-ENCODING: [0x00,0x04,0x20,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 04 20 04 <unknown> sub z23.d, z13.d, z8.d // CHECK-INST: sub z23.d, z13.d, z8.d // CHECK-ENCODING: [0xb7,0x05,0xe8,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: b7 05 e8 04 <unknown> sub z23.s, z13.s, z8.s // CHECK-INST: sub z23.s, z13.s, z8.s // CHECK-ENCODING: [0xb7,0x05,0xa8,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: b7 05 a8 04 <unknown> sub z31.d, z31.d, z31.d // CHECK-INST: sub z31.d, z31.d, z31.d // CHECK-ENCODING: [0xff,0x07,0xff,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 07 ff 04 <unknown> sub z23.h, z13.h, z8.h // CHECK-INST: sub z23.h, z13.h, z8.h // CHECK-ENCODING: [0xb7,0x05,0x68,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: b7 05 68 04 <unknown> sub z0.d, z0.d, z0.d // CHECK-INST: sub z0.d, z0.d, z0.d // CHECK-ENCODING: [0x00,0x04,0xe0,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 04 e0 04 <unknown> sub z31.s, z31.s, z31.s // CHECK-INST: sub z31.s, z31.s, z31.s // CHECK-ENCODING: [0xff,0x07,0xbf,0x04] -// CHECK-ERROR: invalid operand for instruction +// CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 07 bf 04 <unknown> diff --git a/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s b/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s new file mode 100644 index 00000000000..810ba7ac762 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/zip1-diagnostics.s @@ -0,0 +1,43 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Invalid element kind. +zip1 z10.h, z22.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier +// CHECK-NEXT: zip1 z10.h, z22.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +zip1 z10.h, z3.h, z15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: zip1 z10.h, z3.h, z15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Too few operands +zip1 z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction +// CHECK-NEXT: zip1 z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// z32 is not a valid SVE data register +zip1 z1.s, z2.s, z32.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: zip1 z1.s, z2.s, z32.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// p16 is not a valid SVE predicate register +zip1 p1.s, p2.s, p16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: zip1 p1.s, p2.s, p16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining data and predicate registers as operands +zip1 z1.s, z2.s, p3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: zip1 z1.s, z2.s, p3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining predicate and data registers as operands +zip1 p1.s, p2.s, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: zip1 p1.s, p2.s, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/zip1.s b/llvm/test/MC/AArch64/SVE/zip1.s new file mode 100644 index 00000000000..47d08328fd9 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/zip1.s @@ -0,0 +1,104 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +zip1 z0.b, z0.b, z0.b +// CHECK-INST: zip1 z0.b, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x60,0x20,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 20 05 <unknown> + +zip1 z0.h, z0.h, z0.h +// CHECK-INST: zip1 z0.h, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x60,0x60,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 60 05 <unknown> + +zip1 z0.s, z0.s, z0.s +// CHECK-INST: zip1 z0.s, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x60,0xa0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 a0 05 <unknown> + +zip1 z0.d, z0.d, z0.d +// CHECK-INST: zip1 z0.d, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x60,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 e0 05 <unknown> + +zip1 z31.b, z31.b, z31.b +// CHECK-INST: zip1 z31.b, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x63,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 63 3f 05 <unknown> + +zip1 z31.h, z31.h, z31.h +// CHECK-INST: zip1 z31.h, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x63,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 63 7f 05 <unknown> + +zip1 z31.s, z31.s, z31.s +// CHECK-INST: zip1 z31.s, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x63,0xbf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 63 bf 05 <unknown> + +zip1 z31.d, z31.d, z31.d +// CHECK-INST: zip1 z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x63,0xff,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 63 ff 05 <unknown> + +zip1 p0.b, p0.b, p0.b +// CHECK-INST: zip1 p0.b, p0.b, p0.b +// CHECK-ENCODING: [0x00,0x40,0x20,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 20 05 <unknown> + +zip1 p0.h, p0.h, p0.h +// CHECK-INST: zip1 p0.h, p0.h, p0.h +// CHECK-ENCODING: [0x00,0x40,0x60,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 60 05 <unknown> + +zip1 p0.s, p0.s, p0.s +// CHECK-INST: zip1 p0.s, p0.s, p0.s +// CHECK-ENCODING: [0x00,0x40,0xa0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 a0 05 <unknown> + +zip1 p0.d, p0.d, p0.d +// CHECK-INST: zip1 p0.d, p0.d, p0.d +// CHECK-ENCODING: [0x00,0x40,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 40 e0 05 <unknown> + +zip1 p15.b, p15.b, p15.b +// CHECK-INST: zip1 p15.b, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x41,0x2f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 41 2f 05 <unknown> + +zip1 p15.s, p15.s, p15.s +// CHECK-INST: zip1 p15.s, p15.s, p15.s +// CHECK-ENCODING: [0xef,0x41,0xaf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 41 af 05 <unknown> + +zip1 p15.h, p15.h, p15.h +// CHECK-INST: zip1 p15.h, p15.h, p15.h +// CHECK-ENCODING: [0xef,0x41,0x6f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 41 6f 05 <unknown> + +zip1 p15.d, p15.d, p15.d +// CHECK-INST: zip1 p15.d, p15.d, p15.d +// CHECK-ENCODING: [0xef,0x41,0xef,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 41 ef 05 <unknown> diff --git a/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s b/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s new file mode 100644 index 00000000000..af783fcf07a --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/zip2-diagnostics.s @@ -0,0 +1,43 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// Invalid element kind. +zip2 z6.h, z23.h, z31.x +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier +// CHECK-NEXT: zip2 z6.h, z23.h, z31.x +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Element size specifiers should match. +zip2 z0.h, z30.h, z24.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: zip2 z0.h, z30.h, z24.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Too few operands +zip2 z1.h, z2.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction +// CHECK-NEXT: zip2 z1.h, z2.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// z32 is not a valid SVE data register +zip2 z1.s, z2.s, z32.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: zip2 z1.s, z2.s, z32.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// p16 is not a valid SVE predicate register +zip2 p1.s, p2.s, p16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: zip2 p1.s, p2.s, p16.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining data and predicate registers as operands +zip2 z1.s, z2.s, p3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: zip2 z1.s, z2.s, p3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// Combining predicate and data registers as operands +zip2 p1.s, p2.s, z3.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register +// CHECK-NEXT: zip2 p1.s, p2.s, z3.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/zip2.s b/llvm/test/MC/AArch64/SVE/zip2.s new file mode 100644 index 00000000000..3158e989ce7 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/zip2.s @@ -0,0 +1,104 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +zip2 z0.b, z0.b, z0.b +// CHECK-INST: zip2 z0.b, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x64,0x20,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 64 20 05 <unknown> + +zip2 z0.h, z0.h, z0.h +// CHECK-INST: zip2 z0.h, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x64,0x60,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 64 60 05 <unknown> + +zip2 z0.s, z0.s, z0.s +// CHECK-INST: zip2 z0.s, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x64,0xa0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 64 a0 05 <unknown> + +zip2 z0.d, z0.d, z0.d +// CHECK-INST: zip2 z0.d, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x64,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 64 e0 05 <unknown> + +zip2 z31.b, z31.b, z31.b +// CHECK-INST: zip2 z31.b, z31.b, z31.b +// CHECK-ENCODING: [0xff,0x67,0x3f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 67 3f 05 <unknown> + +zip2 z31.h, z31.h, z31.h +// CHECK-INST: zip2 z31.h, z31.h, z31.h +// CHECK-ENCODING: [0xff,0x67,0x7f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 67 7f 05 <unknown> + +zip2 z31.s, z31.s, z31.s +// CHECK-INST: zip2 z31.s, z31.s, z31.s +// CHECK-ENCODING: [0xff,0x67,0xbf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 67 bf 05 <unknown> + +zip2 z31.d, z31.d, z31.d +// CHECK-INST: zip2 z31.d, z31.d, z31.d +// CHECK-ENCODING: [0xff,0x67,0xff,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 67 ff 05 <unknown> + +zip2 p0.b, p0.b, p0.b +// CHECK-INST: zip2 p0.b, p0.b, p0.b +// CHECK-ENCODING: [0x00,0x44,0x20,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 44 20 05 <unknown> + +zip2 p0.h, p0.h, p0.h +// CHECK-INST: zip2 p0.h, p0.h, p0.h +// CHECK-ENCODING: [0x00,0x44,0x60,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 44 60 05 <unknown> + +zip2 p0.s, p0.s, p0.s +// CHECK-INST: zip2 p0.s, p0.s, p0.s +// CHECK-ENCODING: [0x00,0x44,0xa0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 44 a0 05 <unknown> + +zip2 p0.d, p0.d, p0.d +// CHECK-INST: zip2 p0.d, p0.d, p0.d +// CHECK-ENCODING: [0x00,0x44,0xe0,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 44 e0 05 <unknown> + +zip2 p15.b, p15.b, p15.b +// CHECK-INST: zip2 p15.b, p15.b, p15.b +// CHECK-ENCODING: [0xef,0x45,0x2f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 45 2f 05 <unknown> + +zip2 p15.h, p15.h, p15.h +// CHECK-INST: zip2 p15.h, p15.h, p15.h +// CHECK-ENCODING: [0xef,0x45,0x6f,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 45 6f 05 <unknown> + +zip2 p15.s, p15.s, p15.s +// CHECK-INST: zip2 p15.s, p15.s, p15.s +// CHECK-ENCODING: [0xef,0x45,0xaf,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 45 af 05 <unknown> + +zip2 p15.d, p15.d, p15.d +// CHECK-INST: zip2 p15.d, p15.d, p15.d +// CHECK-ENCODING: [0xef,0x45,0xef,0x05] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ef 45 ef 05 <unknown> diff --git a/llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s b/llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s index 5cb10931878..a11a4b227ac 100644 --- a/llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s +++ b/llvm/test/MC/AArch64/armv8.2a-statistical-profiling.s @@ -3,7 +3,7 @@ psb csync // CHECK: psb csync // encoding: [0x3f,0x22,0x03,0xd5] -// NO_SPE: invalid operand for instruction +// NO_SPE: instruction requires: spe msr pmblimitr_el1, x0 msr pmbptr_el1, x0 diff --git a/llvm/test/MC/AArch64/armv8.3a-complex.s b/llvm/test/MC/AArch64/armv8.3a-complex.s index 70dd479235c..1a4975b3e89 100644 --- a/llvm/test/MC/AArch64/armv8.3a-complex.s +++ b/llvm/test/MC/AArch64/armv8.3a-complex.s @@ -133,9 +133,11 @@ // Invalid indices fcmla v0.4h, v1.4h, v2.h[2], #0 -// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1]. +// STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction +// STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1]. fcmla v0.8h, v1.8h, v2.h[4], #0 -// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 3]. +// STDERR-NO-FP16: :[[@LINE-1]]:{{[0-9]*}}: error: invalid operand for instruction +// STDERR-FP16: :[[@LINE-2]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 3]. fcmla v0.4s, v1.4s, v2.s[2], #0 // STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: vector lane must be an integer in range [0, 1]. diff --git a/llvm/test/MC/AArch64/armv8.3a-rcpc.s b/llvm/test/MC/AArch64/armv8.3a-rcpc.s index 0d2da8e2d03..cd254acdf96 100644 --- a/llvm/test/MC/AArch64/armv8.3a-rcpc.s +++ b/llvm/test/MC/AArch64/armv8.3a-rcpc.s @@ -18,9 +18,9 @@ // CHECK: ldapr x0, [x0] // encoding: [0x00,0xc0,0xbf,0xf8] // CHECK: ldapr w18, [x0] // encoding: [0x12,0xc0,0xbf,0xb8] // CHECK: ldapr x15, [x0] // encoding: [0x0f,0xc0,0xbf,0xf8] -// CHECK-REQ: error: invalid operand for instruction -// CHECK-REQ: error: invalid operand for instruction -// CHECK-REQ: error: invalid operand for instruction -// CHECK-REQ: error: invalid operand for instruction +// CHECK-REQ: error: instruction requires: rcpc +// CHECK-REQ: error: instruction requires: rcpc +// CHECK-REQ: error: instruction requires: rcpc +// CHECK-REQ: error: instruction requires: rcpc // CHECK-REQ: error: instruction requires: rcpc // CHECK-REQ: error: instruction requires: rcpc diff --git a/llvm/test/MC/Mips/eva/invalid-noeva-wrong-error.s b/llvm/test/MC/Mips/eva/invalid-noeva-wrong-error.s index 4b725135ef1..3318831b81c 100644 --- a/llvm/test/MC/Mips/eva/invalid-noeva-wrong-error.s +++ b/llvm/test/MC/Mips/eva/invalid-noeva-wrong-error.s @@ -19,51 +19,51 @@ # RUN: FileCheck %s < %t1 .set noat - cachee 31, 255($7) # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offset - cachee 0, -256($4) # CHECK: :[[@LINE]]:22: error: expected memory with 9-bit signed offset - cachee 5, -140($4) # CHECK: :[[@LINE]]:22: error: expected memory with 9-bit signed offset - lbe $10,-256($25) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lbe $13,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lbe $11,146($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lbue $13,-256($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lbue $13,255($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lbue $13,-190($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhe $13,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhe $12,255($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhe $13,81($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhue $s2,-256($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhue $s2,255($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhue $s6,-168($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lle $v0,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lle $v1,255($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lle $v1,-71($s6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwe $15,255($a2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwe $13,-256($a2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwe $15,-200($a1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwle $s6,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwle $s7,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwle $s7,-176($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwre $zero,255($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwre $zero,-256($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwre $zero,-176($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - prefe 14, -256($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - prefe 11, 255($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - prefe 14, -37($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sbe $s1,255($11) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sbe $s1,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sbe $s3,0($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sce $9,255($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sce $12,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sce $13,-31($s7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - she $14,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - she $14,-256($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - she $9,235($11) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swe $ra,255($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swe $ra,-256($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swe $ra,-53($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swle $9,255($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swle $10,-256($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swle $8,131($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $s4,255($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $s4,-256($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $s2,86($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + cachee 31, 255($7) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + cachee 0, -256($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction + cachee 5, -140($4) # CHECK: :[[@LINE]]:22: error: invalid operand for instruction + lbe $10,-256($25) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbe $13,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbe $11,146($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbue $13,-256($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbue $13,255($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbue $13,-190($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $13,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $12,255($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $13,81($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $s2,-256($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $s2,255($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $s6,-168($v0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lle $v0,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lle $v1,255($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lle $v1,-71($s6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwe $15,255($a2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwe $13,-256($a2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwe $15,-200($a1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s6,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s7,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s7,-176($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,255($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-256($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-176($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + prefe 14, -256($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + prefe 11, 255($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + prefe 14, -37($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sbe $s1,255($11) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sbe $s1,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sbe $s3,0($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sce $9,255($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sce $12,-256($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sce $13,-31($s7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + she $14,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + she $14,-256($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + she $9,235($11) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swe $ra,255($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swe $ra,-256($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swe $ra,-53($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $9,255($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $10,-256($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $8,131($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s4,255($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s4,-256($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s2,86($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/eva/invalid.s b/llvm/test/MC/Mips/eva/invalid.s index 406d940c8a9..5c4cc3ddf63 100644 --- a/llvm/test/MC/Mips/eva/invalid.s +++ b/llvm/test/MC/Mips/eva/invalid.s @@ -5,31 +5,31 @@ # RUN: FileCheck %s < %t1 .set noat - cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate - cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate - prefe -1, 255($7) # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate - prefe 32, 255($7) # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + cachee -1, 255($7) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction + cachee 32, 255($7) # CHECK: :[[@LINE]]:12: error: invalid operand for instruction + prefe -1, 255($7) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + prefe 32, 255($7) # CHECK: :[[@LINE]]:11: error: invalid operand for instruction lle $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction - lle $4, 8($33) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - lle $4, 512($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - lle $4, -513($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset + lle $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + lle $4, 512($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + lle $4, -513($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction lwe $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction - lwe $4, 8($33) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - lwe $4, 512($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - lwe $4, -513($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset + lwe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + lwe $4, 512($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + lwe $4, -513($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction sbe $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction - sbe $4, 8($33) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - sbe $4, 512($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - sbe $4, -513($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset + sbe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + sbe $4, 512($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + sbe $4, -513($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction sce $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction - sce $4, 8($33) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - sce $4, 512($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - sce $4, -513($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset + sce $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + sce $4, 512($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + sce $4, -513($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction she $33, 8($5) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction - she $4, 8($33) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - she $4, 512($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - she $4, -513($5) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset + she $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + she $4, 512($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + she $4, -513($5) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction swe $33, 8($4) # CHECK: :[[@LINE]]:9: error: invalid operand for instruction - swe $5, 8($34) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - swe $5, 512($4) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset - swe $5, -513($4) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset + swe $5, 8($34) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + swe $5, 512($4) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + swe $5, -513($4) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/eva/invalid_R6.s b/llvm/test/MC/Mips/eva/invalid_R6.s index b3242e6ffd7..7e99bc28c31 100644 --- a/llvm/test/MC/Mips/eva/invalid_R6.s +++ b/llvm/test/MC/Mips/eva/invalid_R6.s @@ -6,18 +6,18 @@ # RUN: FileCheck %s < %t1 .set noat - lwle $s6,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwle $s7,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwle $s7,-176($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwre $zero,255($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwre $zero,-256($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwre $zero,-176($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swle $9,255($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swle $10,-256($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swle $8,131($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $s4,255($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $s4,-256($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $s2,86($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lwle $s6,255($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s7,-256($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s7,-176($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,255($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-256($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-176($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $9,255($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $10,-256($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $8,131($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s4,255($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s4,-256($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s2,86($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lle $33, 8($5) # CHECK: :[[@LINE]]:19: error: invalid operand for instruction lle $4, 8($33) # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offset lle $4, 512($5) # CHECK: :[[@LINE]]:23: error: expected memory with 9-bit signed offset diff --git a/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s index d1ba873809d..d43ca766fa0 100644 --- a/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s +++ b/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s @@ -4,4 +4,4 @@ .set noat wrdsp $5, 128 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate + wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 7-bit unsigned immediate diff --git a/llvm/test/MC/Mips/micromips/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips/invalid-wrong-error.s index 8d39498bf90..3e4837885a1 100644 --- a/llvm/test/MC/Mips/micromips/invalid-wrong-error.s +++ b/llvm/test/MC/Mips/micromips/invalid-wrong-error.s @@ -6,8 +6,8 @@ # the diagnostic for the 20-bit form. This isn't exactly wrong but it is # misleading. Ideally, we'd emit every way to achieve a valid match instead # of picking only one. - sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 20-bit unsigned immediate + sdbbp -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate sdbbp 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate - syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate + syscall -1 # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate + syscall $4 # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s index 823d3f9a77b..33c5d6595fa 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s @@ -7,38 +7,20 @@ # the diagnostic for the 10-bit form. This isn't exactly wrong but it is # misleading. Ideally, we'd emit every way to achieve a valid match instead # of picking only one. - teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate - teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - tge $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate - tge $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tge $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - tgeu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate - tgeu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tgeu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate - tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate - tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate - tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate - syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset lwc2 $1, -2049($4) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled lwc2 $1, 2048($4) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - lwc2 $1, 16($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset sdc2 $1, -2049($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled sdc2 $1, 2048($16) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - sdc2 $1, 8($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset swc2 $1, -2049($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled swc2 $1, 2048($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled - swc2 $1, 777($32) # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s index 22ec6395cba..218202bc505 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid.s @@ -351,3 +351,21 @@ bnezc $2, -4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address bnezc $2, 4194304 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range bnezc $2, 4194303 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address + teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate + teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate + tge $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate + tge $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate + tgeu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate + tgeu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate + tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate + tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate + tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate + tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 4-bit unsigned immediate + tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate + tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 4-bit unsigned immediate + syscall -1 # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate + syscall $4 # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate + ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset + lwc2 $1, 16($32) # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset + sdc2 $1, 8($32) # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset + swc2 $1, 777($32) # CHECK: :[[@LINE]]:12: error: expected memory with 11-bit signed offset diff --git a/llvm/test/MC/Mips/mips1/invalid-mips2-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips2-wrong-error.s index 5897fb84a20..1b0bcd4f50b 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips2-wrong-error.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips2-wrong-error.s @@ -6,11 +6,11 @@ # RUN: FileCheck %s < %t1 .set noat - ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc2 $8,-1024($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips1/invalid-mips3-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips3-wrong-error.s index d140b258533..b927235e7ca 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips3-wrong-error.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips3-wrong-error.s @@ -6,14 +6,14 @@ # RUN: FileCheck %s < %t1 .set noat - ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips1/invalid-mips3.s b/llvm/test/MC/Mips/mips1/invalid-mips3.s index 42e390df470..6a2543424b8 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips3.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips3.s @@ -54,8 +54,8 @@ floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s index 98f34d857a5..61c9ccaa2c2 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s @@ -8,14 +8,14 @@ .set noat bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips1/invalid-mips4.s b/llvm/test/MC/Mips/mips1/invalid-mips4.s index e99fb6628e6..def3a14e601 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips4.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips4.s @@ -69,8 +69,8 @@ movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5.s b/llvm/test/MC/Mips/mips1/invalid-mips5.s index f909c07f15f..1d7a864d2f5 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips5.s @@ -88,5 +88,5 @@ sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset + ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s index 9aa17b6695b..e99d74ca0f6 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips3-wrong-error.s @@ -9,6 +9,6 @@ dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips2/invalid-mips3.s b/llvm/test/MC/Mips/mips2/invalid-mips3.s index b85204379c7..4bbd486bfd1 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips3.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips3.s @@ -50,8 +50,8 @@ eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:24: error: expected memory with 12-bit signed offset + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:24: error: invalid operand for instruction round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s index 5ced993c2e1..e46aac67cdc 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s @@ -8,6 +8,6 @@ .set noat bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level - scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips2/invalid-mips4.s b/llvm/test/MC/Mips/mips2/invalid-mips4.s index 123235eb00b..04348925cee 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips4.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips4.s @@ -48,7 +48,7 @@ floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: invalid operand for instruction movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s b/llvm/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s index deafbb02eca..6d569d12b39 100644 --- a/llvm/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s +++ b/llvm/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s @@ -11,8 +11,8 @@ lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $24, 5($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $24, 5($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s index b26cc4e2328..aa911be15cb 100644 --- a/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s @@ -11,13 +11,13 @@ bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction ldc2 $1, -2049($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled ldc2 $1, 2048($12) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled - ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset + ldc2 $1, 1023($32) # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset lwc2 $1, -2049($4) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled lwc2 $1, 2048($4) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled - lwc2 $1, 16($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset + lwc2 $1, 16($32) # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset sdc2 $1, -2049($16) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled sdc2 $1, 2048($16) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled - sdc2 $1, 8($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset + sdc2 $1, 8($32) # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset swc2 $1, -2049($17) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled swc2 $1, 2048($17) # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled - swc2 $1, 777($32) # CHECK: :[[@LINE]]:18: error: expected memory with 16-bit signed offset + swc2 $1, 777($32) # CHECK: :[[@LINE]]:18: error: expected memory with 11-bit signed offset diff --git a/llvm/test/MC/Mips/mips32r6/invalid.s b/llvm/test/MC/Mips/mips32r6/invalid.s index fac106fc949..cb950cbd08b 100644 --- a/llvm/test/MC/Mips/mips32r6/invalid.s +++ b/llvm/test/MC/Mips/mips32r6/invalid.s @@ -27,17 +27,17 @@ local_label: lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips64/invalid-mips64r2.s b/llvm/test/MC/Mips/mips64/invalid-mips64r2.s index 4d8411634f2..d8730af4388 100644 --- a/llvm/test/MC/Mips/mips64/invalid-mips64r2.s +++ b/llvm/test/MC/Mips/mips64/invalid-mips64r2.s @@ -29,13 +29,13 @@ seb $25,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seh $v1,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate - dins $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: expected 6-bit unsigned immediate - dinsm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate - dinsm $2, $3, 32, 1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate - dinsm $2, $3, 31, 0 # CHECK: :[[@LINE]]:27: error: expected immediate in range 2 .. 64 - dinsm $2, $3, 31, 65 # CHECK: :[[@LINE]]:27: error: expected immediate in range 2 .. 64 - dinsu $2, $3, 31, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63 - dinsu $2, $3, 64, 1 # CHECK: :[[@LINE]]:23: error: expected immediate in range 32 .. 63 - dinsu $2, $3, 63, 0 # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32 - dinsu $2, $3, 32, 33 # CHECK: :[[@LINE]]:27: error: expected immediate in range 1 .. 32 + dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction + dins $2, $3, 64, 1 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction + dinsm $2, $3, -1, 1 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + dinsm $2, $3, 32, 1 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + dinsm $2, $3, 31, 0 # CHECK: :[[@LINE]]:27: error: invalid operand for instruction + dinsm $2, $3, 31, 65 # CHECK: :[[@LINE]]:27: error: invalid operand for instruction + dinsu $2, $3, 31, 1 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + dinsu $2, $3, 64, 1 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + dinsu $2, $3, 63, 0 # CHECK: :[[@LINE]]:27: error: invalid operand for instruction + dinsu $2, $3, 32, 33 # CHECK: :[[@LINE]]:27: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s b/llvm/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s index 816cc1f8c6c..06d95fd8665 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s +++ b/llvm/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s @@ -11,7 +11,7 @@ lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s b/llvm/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s index bf2d5fa988b..a111726fca3 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s +++ b/llvm/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s @@ -17,7 +17,7 @@ lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips64r6/invalid.s b/llvm/test/MC/Mips/mips64r6/invalid.s index a19181b723f..a7405371182 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid.s +++ b/llvm/test/MC/Mips/mips64r6/invalid.s @@ -57,17 +57,17 @@ local_label: lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset - lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset - lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset + lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction // FIXME: Following tests are temporarily disabled, until "PredicateControl not in hierarchy" problem is resolved bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/msa/invalid.s b/llvm/test/MC/Mips/msa/invalid.s index 78b1949d0ae..ffb5b368d70 100644 --- a/llvm/test/MC/Mips/msa/invalid.s +++ b/llvm/test/MC/Mips/msa/invalid.s @@ -107,22 +107,22 @@ copy_s.h $2, $w9[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate copy_s.w $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate copy_s.w $2, $w9[4] # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate - copy_s.d $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate - copy_s.d $2, $w9[2] # CHECK: :[[@LINE]]:22: error: expected 1-bit unsigned immediate + copy_s.d $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: invalid operand for instruction + copy_s.d $2, $w9[2] # CHECK: :[[@LINE]]:22: error: invalid operand for instruction copy_u.b $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate copy_u.b $2, $w9[16] # CHECK: :[[@LINE]]:22: error: expected 4-bit unsigned immediate copy_u.h $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate copy_u.h $2, $w9[8] # CHECK: :[[@LINE]]:22: error: expected 3-bit unsigned immediate - copy_u.w $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate - copy_u.w $2, $w9[4] # CHECK: :[[@LINE]]:22: error: expected 2-bit unsigned immediate + copy_u.w $2, $w9[-1] # CHECK: :[[@LINE]]:22: error: invalid operand for instruction + copy_u.w $2, $w9[4] # CHECK: :[[@LINE]]:22: error: invalid operand for instruction insert.b $w9[-1], $2 # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate insert.b $w9[16], $2 # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate insert.h $w9[-1], $2 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate insert.h $w9[8], $2 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate insert.w $w9[-1], $2 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate insert.w $w9[4], $2 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate - insert.d $w9[-1], $2 # CHECK: :[[@LINE]]:18: error: expected 1-bit unsigned immediate - insert.d $w9[2], $2 # CHECK: :[[@LINE]]:18: error: expected 1-bit unsigned immediate + insert.d $w9[-1], $2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction + insert.d $w9[2], $2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction insve.b $w25[-1], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate insve.b $w25[16], $w9[0] # CHECK: :[[@LINE]]:18: error: expected 4-bit unsigned immediate insve.h $w24[-1], $w2[0] # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate diff --git a/llvm/test/MC/Mips/target-soft-float.s b/llvm/test/MC/Mips/target-soft-float.s index f532cdf2ed9..5865d5ab126 100644 --- a/llvm/test/MC/Mips/target-soft-float.s +++ b/llvm/test/MC/Mips/target-soft-float.s @@ -269,10 +269,10 @@ foo: # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled ldc1 $f2, 16($7) # FIXME: LDC1 is correctly rejected but the wrong error message is emitted. - # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset + # 32: :[[@LINE-2]]:19: error: invalid operand for instruction lwc1 $f2, 16($7) # FIXME: LWC1 is correctly rejected but the wrong error message is emitted. - # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset + # 32: :[[@LINE-2]]:19: error: invalid operand for instruction madd.s $f2, $f2, $f2, $f2 # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled mfc1 $7, $f2 @@ -313,7 +313,7 @@ foo: # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled sdc1 $f2, 16($7) # FIXME: SDC1 is correctly rejected but the wrong error message is emitted. - # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset + # 32: :[[@LINE-2]]:19: error: invalid operand for instruction sqrt.d $f2, $f2 # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled sqrt.s $f2, $f2 @@ -324,7 +324,7 @@ foo: # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled swc1 $f2, 16($7) # FIXME: SWC1 is correctly rejected but the wrong error message is emitted. - # 32: :[[@LINE-2]]:19: error: expected memory with 16-bit signed offset + # 32: :[[@LINE-2]]:19: error: invalid operand for instruction trunc.w.d $f2, $f2 # 32: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled trunc.w.s $f2, $f2 |
