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* [mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocationsSimon Atanasyan2018-05-291-2/+12
| | | | | | | | | | | Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations for %higher() and %highest() expressions in case of microMIPS. These relocations do exactly the same things as R_MIPS_HIGHER / R_MIPS_HIGHEST, but for consistency it's better to write microMIPS variants. Differential Revision: http://reviews.llvm.org/D47219 llvm-svn: 333407
* [mips] Correct the predicates for a number of instructions.Simon Dardis2018-05-297-14/+30
| | | | | | | | | | Previously, their listed predicates were overridden at the scope level. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46947 llvm-svn: 333405
* [mips] Stop parsing a .set assignment if the first argument is not an identifierSimon Atanasyan2018-05-291-0/+10
| | | | | | | | | | | | | | Before this fix the following code triggers two error messages. The second one is at least useless: test.s:1:9: error: expected identifier after .set .set 123, $a0 ^ test-set.s:1:9: error: unexpected token, expected comma .set 123, $a0 ^ llvm-svn: 333402
* [PowerPC] Set isAsmParserOnly=1 for X-form TLS loads/storesZaara Syeda2018-05-281-1/+20
| | | | | | | | | | | | The X-form TLS load/store instructions added for optimizing the initial-exec sequence in https://reviews.llvm.org/rL327635 fail to assemble. llvm-mc fails with the error: invalid operand for instruction. This patch adds these instructions into a block with isAsmParserOnly, similar to how ADD8TLS_ is currently handled. Differential Revision: https://reviews.llvm.org/D47382 llvm-svn: 333374
* [Sparc] Add .uahalf and .uaword directivesDaniel Cederman2018-05-281-0/+6
| | | | | | | | | | | | | | | | | | | | | | Summary: Adding these makes it easier to assemble the output from GCC which generates a lot of .uahalf and .uaword directives. GAS treats .uahalf and .half the same unless the --enforce-aligned-data flag is used. I could not find a similar flag for LLVM so it seems that .half does not have any alignment requirement and is treated the same as .uahalf should be. If that would change later on then the tests in sparc-directives.s would fail due to bad alignment. Reviewers: jyknight, asb Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D47319 llvm-svn: 333372
* [AArch64][SVE] Asm: Support for DUP (immediate) instructions.Sander de Smalen2018-05-254-0/+490
| | | | | | | | | | | | | | | | | | | | | | | | | | Unpredicated copy of optionally-shifted immediate to SVE vector, along with MOV-aliases. This patch contains parsing and printing support for cpy_imm8_opt_lsl_(i8|i16|i32|i64). This operand allows a signed value in the range -128 to +127. For element widths of 16 bits or higher it may also be a signed multiple of 256 in the range -32768 to +32512. For element-width of 8 bits a range of -128 to 255 is accepted, since a copy of a byte can be considered either signed/unsigned. Note: This patch renames tryParseAddSubImm() -> tryParseImmWithOptionalShift() and moves the behaviour of trying to shift a plain immediate by an allowed shift-value to its addImmWithOptionalShiftOperands() method, so that the parsing itself is generic and allows immediates from multiple shifted operands. This is done because an immediate can be divisible by both shifted operands. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47309 llvm-svn: 333263
* [RISCV] Support linker relax function call from auipc and jalr to jalShiva Chen2018-05-241-0/+26
| | | | | | | | | | | | | To do this: 1. Add fixup_riscv_relax fixup types which eventually will transfer to R_RISCV_RELAX relocation types. 2. Insert R_RISCV_RELAX relocation types to auipc function call expression when linker relaxation enabled. Differential Revision: https://reviews.llvm.org/D44886 llvm-svn: 333158
* [RISCV] Add symbol diff relocation support for RISC-VAlex Bradbury2018-05-233-24/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For RISC-V it is desirable to have relaxation happen in the linker once addresses are known, and as such the size between two instructions/byte sequences in a section could change. For most assembler expressions, this is fine, as the absolute address results in the expression being converted to a fixup, and finally relocations. However, for expressions such as .quad .L2-.L1, the assembler folds this down to a constant once fragments are laid out, under the assumption that the difference can no longer change, although in the case of linker relaxation the differences can change at link time, so the constant is incorrect. One place where this commonly appears is in debug information, where the size of a function expression is in a form similar to the above. This patch extends the assembler to allow an AsmBackend to declare that it does not want the assembler to fold down this expression, and instead generate a pair of relocations that allow the linker to carry out the calculation. In this case, the expression is not folded, but when it comes to emitting a fixup, the generic FK_Data_* fixups are converted into a pair, one for the addition half, one for the subtraction, and this is passed to the relocation generating methods as usual. I have named these FK_Data_Add_* and FK_Data_Sub_* to indicate which half these are for. For RISC-V, which supports this via e.g. the R_RISCV_ADD64, R_RISCV_SUB64 pair of relocations, these are also set to always emit relocations relative to local symbols rather than section offsets. This is to deal with the fact that if relocations were calculated on e.g. .text+8 and .text+4, the result 12 would be stored rather than 4 as both addends are added in the linker. Differential Revision: https://reviews.llvm.org/D45181 Patch by Simon Cook. llvm-svn: 333079
* [Sparc] Add mnemonic aliases for flush, stb, stba, sth, and sthaDaniel Cederman2018-05-231-0/+18
| | | | | | | | | | | | Reviewers: jyknight Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D47140 llvm-svn: 333068
* [mips] Correct the predicates of the cache and pref instructionsSimon Dardis2018-05-223-0/+6
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46949 llvm-svn: 332970
* MC: Introduce an ELF dwo object writer and teach llvm-mc about it.Peter Collingbourne2018-05-212-0/+35
| | | | | | | | Part of PR37466. Differential Revision: https://reviews.llvm.org/D47051 llvm-svn: 332875
* [mips] Add microMIPSR6 ll/sc instructions.Simon Dardis2018-05-204-0/+18
| | | | | | | | | | Previously the compiler was using the microMIPSR3 variants, incorrectly. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46948 llvm-svn: 332820
* [MC] Relax .fill size requirementsNirav Dave2018-05-184-8/+87
| | | | | | | | | | | | | | | Avoid requirement that number of values must be known at assembler time. Fixes PR33586. Reviewers: rnk, peter.smith, echristo, jyknight Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D46703 llvm-svn: 332741
* [RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvancedShiva Chen2018-05-183-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
* [RISCV] Implement MC layer support for the tail pseudoinstructionMandeep Singh Grang2018-05-172-0/+59
| | | | | | | | | | | | | | | | Summary: This patch implements MC support for tail psuedo instruction. A follow-up patch implements the codegen support as well as handling of the indirect tail pseudo instruction. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, llvm-commits Differential Revision: https://reviews.llvm.org/D46221 llvm-svn: 332634
* [mips] Add support for Global INValidate ASEPetar Jovanovic2018-05-1711-0/+114
| | | | | | | | | | | | | | | | | | This includes Instructions: ginvi, ginvt, Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv Attribute: ginv .MIPS.abiflags: GINV (0x20000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D46268 llvm-svn: 332624
* [Hexagon] Use addAliasForDirective for data directivesAlex Bradbury2018-05-172-0/+45
| | | | | | | | | | | Data directives such as .word, .half, .hword are currently parsed using HexagonAsmParser::ParseDirectiveValue which effectively duplicates logic from AsmParser::parseDirectiveValue. This patch deletes that duplicated logic in favour of using addAliasForDirective. Differential Revision: https://reviews.llvm.org/D46999 llvm-svn: 332607
* [AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 (scalar+scalar) ↵Sander de Smalen2018-05-1724-0/+478
| | | | | | | | | | | | store instructions. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46680 llvm-svn: 332584
* [RISCV] Add support for .half, .hword, .word, .dword directivesAlex Bradbury2018-05-172-0/+55
| | | | | | | | | | These directives are recognised by gas. Support is added through the use of addAliasForDirective. Also match RISC-V gcc in preferring .half and .word for 16-bit and 32-bit data directives. llvm-svn: 332574
* [WebAssembly] MC: Ensure that FUNCTION_OFFSET relocations are always against ↵Sam Clegg2018-05-161-3/+10
| | | | | | | | | | | | | | | | | function symbols. The getAtom() method wasn't doing what we needed in all cases. We want the symbols for the function which defines that section. We can compute this easily enough and we know that we have at most one function in each section. Once this lands I will revert rL331412 which is no longer needed. Fixes PR37409 Differential Revision: https://reviews.llvm.org/D46970 llvm-svn: 332517
* [AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.Sander de Smalen2018-05-1647-153/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For regular SVE vector operands, this patch introduces a more sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b). For example: add z0.s, z1.s, z2.b -> invalid element width ^_____^ mismatch For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes a slightly different approach and instead returns a 'invalid operand' if the element size is not as expected. This is because the diagnostics are more specificied to suggest using the right shift/extend suffix. This is a trade-off not to introduce more operand classes and still provide useful diagnostics for LD1 and PRF instructions. For example: ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)' ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand ^________________^ mismatch For gather prefetches, both 'z0.s' and 'z0.d' would be allowed: prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2' prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' Without this change, the diagnostic would unnecessarily suggest a different element size: prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2' Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46688 llvm-svn: 332483
* [AArch64][SVE] Asm: Support for gather PRF prefetch instructionsSander de Smalen2018-05-168-4/+525
| | | | | | | | | | Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46686 llvm-svn: 332472
* [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) ↵Sander de Smalen2018-05-1624-0/+477
| | | | | | | | | | | | load instructions. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46679 llvm-svn: 332442
* [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions.Sander de Smalen2018-05-169-1/+1029
| | | | | | | | | | Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46682 llvm-svn: 332433
* AMDGPU: Fix v_dot{4, 8}* instruction encodingKonstantin Zhuravlyov2018-05-152-12/+512
| | | | | | Differential Revision: https://reviews.llvm.org/D46848 llvm-svn: 332387
* AMDGPU: Add disasm tests for deep learning instructions + fix v_fmac_f32 disasmKonstantin Zhuravlyov2018-05-151-0/+973
| | | | | | Differential Revision: https://reviews.llvm.org/D46853 llvm-svn: 332377
* [mips] Mark select instructions correctlySimon Dardis2018-05-151-2/+10
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46702 llvm-svn: 332364
* [mips] Add disassembly support for comparison instructionsSimon Dardis2018-05-152-0/+192
| | | | llvm-svn: 332340
* [mips] Fix predicates of mfc1, mtc1 instructionsSimon Dardis2018-05-155-0/+24
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46692 llvm-svn: 332339
* Hexagon: Put relocations after instructions not packets.Sid Manning2018-05-142-2/+17
| | | | | | | | | | | | | Change relocation output so that relocation information follows individual instructions rather than clustering them at the end of packets. This change required shifting block of code but the actual change is in HexagonPrettyPrinter's PrintInst. Differential Revision: https://reviews.llvm.org/D46728 llvm-svn: 332283
* [mips] Fix the predicates of round, ceiling, floor and trunc.Simon Dardis2018-05-1417-72/+223
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
* [mips] Add missing test case from r332227Simon Dardis2018-05-141-0/+26
| | | | | | I did not commit this test from D46689. llvm-svn: 332241
* [mips] Correct the predicates of indexed floating point stores and loads.Simon Dardis2018-05-143-6/+4
| | | | | | | | | | Also, fix the register class for microMIPS. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46689 llvm-svn: 332227
* Correct compatibility with the GNU Assembler's handling of comparison opsBill Wendling2018-05-143-11/+21
| | | | | | | | GAS returns -1 for a comparison operator if the result is true and 0 if false. https://www.sourceware.org/binutils/docs-2.12/as.info/Infix-Ops.html#Infix%20Ops llvm-svn: 332215
* [RISCV] Support .option rvc and norvc assembler directivesAlex Bradbury2018-05-112-0/+107
| | | | | | | | | | These directives allow the 'C' (compressed) extension to be enabled/disabled within a single file. Differential Revision: https://reviews.llvm.org/D45864 Patch by Kito Cheng llvm-svn: 332107
* [mips] Enable disassembly of fused (negative) multiply add/sub instructionsSimon Dardis2018-05-113-0/+23
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46392 llvm-svn: 332097
* [WebAssembly] Initial Disassembler.Sam Clegg2018-05-102-0/+36
| | | | | | | | | | | | | | | | | | | | | This implements a new table-gen emitter to create tables for a wasm disassembler, and a dissassembler to use them. Comes with 2 tests, that tests a few instructions manually. Is also able to disassemble large .wasm files with objdump reasonably. Not working so well, to be addressed in followups: - objdump appears to be passing an incorrect starting point. - since the disassembler works an instruction at a time, and it is disassembling stack instruction, it has no idea of pseudo register assignments. These registers are required for the instruction printing code that follows. For now, all such registers appear in the output as $0. Patch by Wouter van Oortmerssen Differential Revision: https://reviews.llvm.org/D45848 llvm-svn: 332052
* [WebAsembly] Update default triple in test files to wasm32-unknown-unkown.Sam Clegg2018-05-1025-25/+25
| | | | | | | | | | Summary: The final -wasm component has been the default for some time now. Subscribers: jfb, dschuff, jgravelle-google, eraman, aheejin, JDevlieghere, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D46342 llvm-svn: 332007
* [mips] Accept 32-bit offsets for ld/sd/lld commandsSimon Atanasyan2018-05-102-6/+38
| | | | | | | | | | | | This is a follow up to the rL330983. The patch teaches ld, sd, and lld commands accept 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. In fact, these commands should accept 64-bit offsets, but so large offsets require another command expanding and will be supported by a separate patch. Differential Revision: https://reviews.llvm.org/D46629 llvm-svn: 331997
* [mips] Accept 32-bit offsets for lh and lhu commandsSimon Atanasyan2018-05-106-16/+52
| | | | | | | | | | This is a follow up to the rL330983. The patch teaches lh and lhu commands accepts 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. Differential Revision: https://reviews.llvm.org/D46513 llvm-svn: 331996
* [mips] Correct the predicates of cvt.fmt.fmt instructionsSimon Dardis2018-05-1011-72/+156
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46390 llvm-svn: 331969
* [mips] Move conditional moves out of isCodeGenOnlySimon Dardis2018-05-093-0/+32
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46389 llvm-svn: 331863
* [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen2018-05-097-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to set breakpoints on labels and list source code around labels, we need collect debug information for labels, i.e., label name, the function label belong, line number in the file, and the address label located. In order to keep these information in LLVM IR and to allow backend to generate debug information correctly. We create a new kind of metadata for labels, DILabel. The format of DILabel is !DILabel(scope: !1, name: "foo", file: !2, line: 3) We hope to keep debug information as much as possible even the code is optimized. So, we create a new kind of intrinsic for label metadata to avoid the metadata is eliminated with basic block. The intrinsic will keep existing if we keep it from optimized out. The format of the intrinsic is llvm.dbg.label(metadata !1) It has only one argument, that is the DILabel metadata. The intrinsic will follow the label immediately. Backend could get the label metadata through the intrinsic's parameter. We also create DIBuilder API for labels to be used by Frontend. Frontend could use createLabel() to allocate DILabel objects, and use insertLabel() to insert llvm.dbg.label intrinsic in LLVM IR. Differential Revision: https://reviews.llvm.org/D45024 Patch by Hsiangkai Wang. llvm-svn: 331841
* [AArch64][SVE] Asm: Support for LD1R load-and-replicate scalar instructions.Sander de Smalen2018-05-0814-0/+548
| | | | | | | | | | Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46251 llvm-svn: 331758
* [mips] Mark various memory instructions as being in microMIPS (NFC)Simon Dardis2018-05-081-2/+44
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46388 llvm-svn: 331756
* [AArch64] Disallow vector operand if FPR128 Q register is required.Sander de Smalen2018-05-081-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | Patch https://reviews.llvm.org/D41445 changed the behaviour of 'isReg()' to also return 'true' if the parsed register operand is a vector register. Code in the AsmMatcher checks if a register is a subclass of the expected register class. However, even though both parsed registers map to the same physical register, the 'v' register is of kind 'NeonVector', where 'q' is of type Scalar, where isSubclass() does not distinguish between the two cases. The solution is to use an AsmOperand instead of the register directly, and use the PredicateMethod to distinguish the two operands. This fixes for example: ldr v0, [x0] // 'v0' is an invalid operand for this instruction ldr q0, [x0] // valid Reviewers: aemerson, Gerolf, SjoerdMeijer, javed.absar Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D46310 llvm-svn: 331755
* [mips] Correct clo/clz predicatesSimon Dardis2018-05-086-0/+12
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46125 llvm-svn: 331754
* [x86] Introduce the enclv instructionGabor Buella2018-05-087-29/+42
| | | | | | | | | | | | | | Summary: and use the -msgx flag as a requirement for the SGX instructions. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46436 llvm-svn: 331742
* [x86] Introduce the pconfig instructionGabor Buella2018-05-084-0/+14
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46430 llvm-svn: 331739
* [Hexagon] Move clamping of extended operands directly to MC code emitterKrzysztof Parzyszek2018-05-071-0/+7
| | | | llvm-svn: 331653
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