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| author | Simon Dardis <simon.dardis@mips.com> | 2018-05-20 17:21:00 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@mips.com> | 2018-05-20 17:21:00 +0000 |
| commit | 777afc7fbd903f21ba575c800172bca779e264ff (patch) | |
| tree | 80f3a46cdb426466f253498b4e0b96bed3ba7b22 /llvm/test/MC | |
| parent | a003c728a52a77cf585453313b601edaf5a19225 (diff) | |
| download | bcm5719-llvm-777afc7fbd903f21ba575c800172bca779e264ff.tar.gz bcm5719-llvm-777afc7fbd903f21ba575c800172bca779e264ff.zip | |
[mips] Add microMIPSR6 ll/sc instructions.
Previously the compiler was using the microMIPSR3 variants, incorrectly.
Reviewers: atanasyan, abeserminji, smaksimovic
Differential Revision: https://reviews.llvm.org/D46948
llvm-svn: 332820
Diffstat (limited to 'llvm/test/MC')
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/invalid.s | 8 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/valid.s | 2 |
4 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt index 00ec2be9a34..4b3bff5484f 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -351,3 +351,7 @@ 0xf4 0x40 0x00 0x40 # CHECK: blezc $2, 260 0xf6 0x10 0x00 0x80 # CHECK: bgezc $16, 516 0xd5 0x80 0x01 0x00 # CHECK: bgtzc $12, 1028 +0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4) +0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4) +0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4) +0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4) diff --git a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s index 33c5d6595fa..8bccb4c2b28 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s @@ -24,3 +24,7 @@ swc2 $1, 2048($17) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled lwc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sc $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + sc $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + ll $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + ll $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s index e49431e71db..e301ee0cb3a 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid.s @@ -154,6 +154,10 @@ sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + ll $33, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number + ll $4, 8($33) # CHECK: :[[@LINE]]:12: error: invalid register number + ll $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + ll $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled lle $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number lle $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number lle $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset @@ -166,6 +170,10 @@ sbe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number sbe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset sbe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset + sc $33, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number + sc $4, 8($33) # CHECK: :[[@LINE]]:12: error: invalid register number + sc $4, 512($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + sc $4, -513($5) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled sce $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number sce $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index e56138e66ff..74efdab0296 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -74,6 +74,7 @@ lwm $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22] ll $2, 8($4) # CHECK: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] + # CHECK-NEXT: # <MCInst #{{.*}} LL_MMR6 lwm32 $16, $17, 8($4) # CHECK: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08] lwm32 $16, $17, 8($sp) # CHECK: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08] lwm32 $16, $17, $ra, 8($4) # CHECK: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08] @@ -88,6 +89,7 @@ rotr $9, $6, 7 # CHECK: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0] rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0] sc $2, 8($4) # CHECK: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08] + # CHECK-NEXT: # <MCInst #{{.*}} SC_MMR6 sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x50] sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xa6,0x23,0x90] sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0x85,0x20,0x10] |
