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* [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, D...Zlatko Buljan2016-04-132-8/+8
* [mips] add assembler support for .set arch=octeonPetar Jovanovic2016-04-121-2/+4
* Revert "[mips] MIPSR6 Compact branch aliases"Simon Dardis2016-04-126-12/+0
* [mips] MIPSR6 Compact branch aliasesSimon Dardis2016-04-126-0/+12
* MCParser: diagnose missing directional labels more clearly.Tim Northover2016-04-114-6/+18
* [mips] Trivial corrections to range checked immediates.Daniel Sanders2016-04-114-0/+8
* [SystemZ] Add SVC instructionUlrich Weigand2016-04-112-0/+22
* [ARM] Avoid switching ARM/Thumb mode on .arch/.cpu directiveOliver Stannard2016-04-111-0/+52
* [X86] Restrict max long nop length for Lakemont.Andrey Turetskiy2016-04-111-9/+11
* [MC] support TLSDESC and TLSCALL / GNU2 tls dialectDavide Italiano2016-04-091-0/+26
* Revert r265817Colin LeMahieu2016-04-0838-50/+49
* [llvm-objdump] Printing hex instead of dec by defaultColin LeMahieu2016-04-0838-49/+50
* [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* instru...Zlatko Buljan2016-04-082-0/+45
* [AMDGPU] Add some VI disassembler tests missing from previous autogeneration ...Valery Pykhtin2016-04-081-0/+66
* [AMDGPU] fix readlane/readfirstlane src vgpr operand type.Valery Pykhtin2016-04-072-2/+5
* [AMDGPU] AsmParser: disable DPP for unsupported instructions. New dpp tests. ...Sam Kolton2016-04-061-12/+363
* [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random nu...Chuang-Yu Cheng2016-04-063-0/+111
* [Power9] Implement copy-paste, msgsync, slb, and stop instructionsChuang-Yu Cheng2016-04-063-0/+65
* [mips] MIPSR6 Compact jump supportSimon Dardis2016-04-051-0/+2
* [mips] Range check simm32 and fold MIPS16's imm32 into simm32.Daniel Sanders2016-04-041-12/+6
* [SystemZ] Add compare-and-branch instructions to MCUlrich Weigand2016-04-042-0/+1176
* [mips][microMIPS] Revert commits r264245 and r264248.Zoran Jovanovic2016-04-022-8/+8
* AArch64: support .cpu directiveSaleem Abdulrasool2016-04-021-0/+63
* Add missing emissionKind flags to the DICompileUnits of several old testcases.Adrian Prantl2016-04-011-1/+1
* [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields.Valery Pykhtin2016-04-011-8/+8
* [MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISASagar Thakur2016-04-012-0/+4
* Fix for pr24346: arm asm label calculation error in subJames Molloy2016-04-013-0/+36
* [AArch64] Better errors for out-of-range fixupsOliver Stannard2016-04-012-1/+65
* testcase gardening: update the emissionKind enum to the new syntax. (NFC)Adrian Prantl2016-04-013-3/+3
* [lanai] isBrImm should accept any non-constant immediate.Jacques Pienaar2016-03-311-0/+13
* [PPC] basic support for Power 9 direct move instructionsEhsan Amiri2016-03-312-0/+22
* [AMDGPU] enable few disassembler tests that were mistakenly marked as FIXME.Valery Pykhtin2016-03-311-8/+8
* [PowerPC] Basic support for P9 atomic loads and storesNemanja Ivanovic2016-03-314-0/+42
* [mips] Range check simm16Daniel Sanders2016-03-315-14/+18
* [mips] Range check simm11 and mem_simm11.Daniel Sanders2016-03-314-8/+16
* [AMDGPU] Disassembler: support for DPPSam Kolton2016-03-311-0/+89
* [mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]Daniel Sanders2016-03-312-50/+39
* [mips] Range check simm9 and fix a bug this revealed.Daniel Sanders2016-03-3112-93/+100
* [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructionsZlatko Buljan2016-03-316-14/+44
* [SystemZ] Add nop and nopr InstAliases.Jonas Paulsson2016-03-301-0/+6
* Handle section vs global name conflict.Evgeniy Stepanov2016-03-282-6/+138
* Sparc: silently ignore .proc assembler directiveDouglas Katzman2016-03-281-0/+4
* [lanai] Add Lanai backend.Jacques Pienaar2016-03-284-0/+1598
* [Power9] Implement new altivec instructions: bcd* seriesChuang-Yu Cheng2016-03-282-0/+86
* [Power9] Implement new vsx instructions: insert, extract, test data class, mi...Chuang-Yu Cheng2016-03-282-0/+210
* [Power9] Implement new vsx instructions: quad-precision move, fp-arithmeticChuang-Yu Cheng2016-03-282-0/+140
* [Power9] Implement new altivec instructions: permute, count zero, extend sign...Chuang-Yu Cheng2016-03-262-0/+187
* [MC][mips] Add MipsMCInstrAnalysis class and register it as MC instruction an...Simon Atanasyan2016-03-241-0/+36
* [llvm-readobj] Decode st_other symbol's flagsSimon Atanasyan2016-03-247-14/+25
* [mips] Range check vsplat_simm5 and vsplat_simm10Daniel Sanders2016-03-241-208/+256
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