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* [MC] Fix compiler crash in AsmParser::LexNirav Dave2017-06-091-0/+4
| | | | | | | | | | | | | | | | When an empty comment is present in an assembly file, the compiler will crash because it checks the first character for '\n' or '\r'. The fix consists of also checking if the string is empty before accessing the *front* method of the StringRef. A test is included for the x86 target, but this issue is reproducible with other targets as well. Patch by Alexandru Guduleasa! Reviewers: niravd, grosbach, llvm-commits Reviewed By: niravd Differential Revision: https://reviews.llvm.org/D33993 llvm-svn: 305077
* [MachO] Fix codegen of alias of alias.Evgeniy Stepanov2017-06-082-4/+16
| | | | | | Fixes PR33316. llvm-svn: 305012
* [AMDGPU][MC] Corrected error message for s_waitcnt helpersDmitry Preobrazhensky2017-06-071-4/+4
| | | | | | | | | | See Bug 32711: https://bugs.llvm.org//show_bug.cgi?id=32711 Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D33781 llvm-svn: 304922
* [mips][dsp] Modify repl.ph to accept signed immediate valuesPetar Jovanovic2017-06-074-4/+6
| | | | | | | | | | | | Changed immediate type for repl.ph from uimm10 to simm10 as per the specs. Repl.qb still accepts uimm8. Both instructions now mimic the behaviour of GNU as. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33594 llvm-svn: 304918
* [ARM] Create relocations for unconditional branches.Florian Hahn2017-06-071-0/+25
| | | | | | | | | | | | | | | | | | | Summary: Relocations are required for unconditional branches to function symbols with different execution mode. Without this patch, incorrect branches are generated for tail calls between functions with different execution mode. Reviewers: peter.smith, rafael, echristo, kristof.beyls Reviewed By: peter.smith Subscribers: aemerson, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33898 llvm-svn: 304882
* [WebAssembly] MC: Refactor relocation handlingSam Clegg2017-06-061-10/+10
| | | | | | | | | | | | | The change cleans up and unifies the handling of relocation entries in WasmObjectWriter. Type index relocation no longer need to be handled separately. The only externally visible change should be that type index relocations are no longer grouped at the end. Differential Revision: https://reviews.llvm.org/D33918 llvm-svn: 304816
* Move ARM specific test to ELF/ARM dirJaved Absar2017-06-051-0/+0
| | | | | | | | | | | Moving ARM specific test clang-section.s from MC/ELF to MC/ELF/ARM Buildbots reported failures on commit https://reviews.llvm.org/rL304705 Full details are available at: http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/10333 llvm-svn: 304706
* Add support for #pragma clang sectionJaved Absar2017-06-051-0/+399
| | | | | | | | | | | | | | | This patch provides a means to specify section-names for global variables, functions and static variables, using #pragma directives. This feature is only defined to work sensibly for ELF targets. One can specify section names as: #pragma clang section bss="myBSS" data="myData" rodata="myRodata" text="myText" One can "unspecify" a section name with empty string e.g. #pragma clang section bss="" data="" text="" rodata="" Reviewers: Roger Ferrer, Jonathan Roelofs, Reid Kleckner Differential Revision: https://reviews.llvm.org/D33413 llvm-svn: 304704
* [ARM] Support fixup for Thumb2 modified immediatePeter Smith2017-06-055-2/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a new fixup fixup_t2_so_imm for the t2_so_imm_asmoperand "T2SOImm". The fixup permits code such as: .L1: sub r3, r3, #.L2 - .L1 .L2: to assemble in Thumb2 as well as in ARM state. The operand predicate isT2SOImm() explicitly doesn't match expressions containing :upper16: and :lower16: as expressions with these operators must match the movt and movw instructions. The test mov r0, foo2 in thumb2-diagnostics is moved to a new file as the fixup delays the error message till after the assembler has quit due to the other errors. As the mov instruction shares the t2_so_imm_asmoperand mov instructions with a non constant expression now match t2MOVi rather than t2MOVi16 so the error message is slightly different. Fixes PR28647 Differential Revision: https://reviews.llvm.org/D33492 llvm-svn: 304702
* [WebAssembly] MC: Fix references to undefined externals in data sectionSam Clegg2017-06-021-0/+21
| | | | | | | | | | | | Undefined externals don't need to have a size or an offset. This was broken by r303915. Added a test for this case. This fixes the "Compile LLVM Torture (o)" step on the wasm waterfall. Differential Revision: https://reviews.llvm.org/D33803 llvm-svn: 304505
* [ARM] Create relocations for Thumb functions calling ARM fns in ELF.Florian Hahn2017-06-012-0/+78
| | | | | | | | | | | | | | | | Summary: Without using a fixup in this case, BL will be used instead of BLX to call internal ARM functions from Thumb functions. Reviewers: rafael, t.p.northover, peter.smith, kristof.beyls Reviewed By: peter.smith Subscribers: srhines, echristo, aemerson, rengolin, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33436 llvm-svn: 304413
* [AMDGPU][MC] New syntax for ds_swizzle_b32 offsetDmitry Preobrazhensky2017-05-313-14/+240
| | | | | | | | | | See Bug 28601: https://bugs.llvm.org//show_bug.cgi?id=28601 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33542 llvm-svn: 304309
* [SystemZ] Add decimal floating-point instructionsUlrich Weigand2017-05-3010-0/+3933
| | | | | | | | | This adds assembler / disassembler support for the decimal floating-point instructions. Since LLVM does not yet have support for decimal float types, these cannot be used for codegen at this point. llvm-svn: 304203
* [SystemZ] Add hexadecimal floating-point instructionsUlrich Weigand2017-05-303-1/+3513
| | | | | | | | This adds assembler / disassembler support for the hexadecimal floating-point instructions. Since the Linux ABI does not use any hex float data types, these are not useful for codegen. llvm-svn: 304202
* [SystemZ] Add missing assembler/disassembler testsUlrich Weigand2017-05-303-0/+148
| | | | | | | A few instructions that are actually correctly supported in the assembler and disassembler did not have any tests. llvm-svn: 304200
* [MC] Fix constant pools with DenseMap sentinel valuesOliver Stannard2017-05-301-0/+12
| | | | | | | | | | | | | The MC ConstantPool class uses a DenseMap to track generated constants, with the int64_t value of the constant as the key. This fails when values of 0x7fffffffffffffff or 0x7ffffffffffffffe are inserted into the constant pool, as these are sentinel values for DenseMap. The fix is to use std::map instead, which doesn't use sentinel values. Differential revision: https://reviews.llvm.org/D33667 llvm-svn: 304199
* [mips] Expansion of LI.S and LI.DZoran Jovanovic2017-05-302-0/+641
| | | | | | | | | Author: smaksimovic Reviewers: dsanders sdardis Introduces LI.S and LI.D pseudo instructions with floating point operands. Differential Revision: https://reviews.llvm.org/D14390 llvm-svn: 304198
* [AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* for SDWA opcodesDmitry Preobrazhensky2017-05-261-0/+4
| | | | | | | | | | See bug 33171: https://bugs.llvm.org/show_bug.cgi?id=33171 Reviewers: Sam Kolton Differential Revision: https://reviews.llvm.org/D33553 llvm-svn: 304015
* [AMDGPU] SDWA: add disassembler support for GFX9Sam Kolton2017-05-261-0/+477
| | | | | | | | | | | | Summary: Added decoder methods and tests Reviewers: vpykhtin, artem.tamazov, dp Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D33545 llvm-svn: 303999
* The fix for PR22004: X86AsmParser.cpp asserts: OperandStack.size() > 1 && ↵Andrew V. Tischenko2017-05-261-0/+3
| | | | | | "Too few operands." llvm-svn: 303985
* [WebAssembly] MC: Include unnamed data when writing wasm filesSam Clegg2017-05-251-0/+53
| | | | | | | | | | | | Also, include global entries for all data symbols, not just external ones, since these are referenced by the relocation records. Add a test case that includes unnamed data. Differential Revision: https://reviews.llvm.org/D33079 llvm-svn: 303915
* [X86] Adding vpopcntd and vpopcntq instructionsOren Ben Simhon2017-05-252-0/+248
| | | | | | | | | AVX512_VPOPCNTDQ is a new feature set that was published by Intel. The patch represents the LLVM side of the addition of two new intrinsic based instructions (vpopcntd and vpopcntq). Differential Revision: https://reviews.llvm.org/D33169 llvm-svn: 303858
* [AMDGPU] SDWA: Add assembler support for GFX9Sam Kolton2017-05-231-169/+268
| | | | | | | | | | | | | | | Summary: Added separate pseudo and real instruction for GFX9 SDWA instructions. Currently supports only in assembler. Depends D32493 Reviewers: vpykhtin, artem.tamazov Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D33132 llvm-svn: 303620
* Re-apply r302416: [ARM] Clear the constant pool cache on explicit .ltorg ↵James Molloy2017-05-221-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | directives Re-applying now that PR32825 which was raised on the commit this fixed up is now known to have also been fixed by this commit. Original commit message: Multiple ldr pseudoinstructions with the same constant value will reuse the same constant pool entry. However, if the constant pool is explicitly flushed with a .ltorg directive, we should not try to reference constants in the previous pool any longer, since they may be out of range. This fixes assembling hand-written assembler source which repeatedly loads the same constant value, across a binary size larger than the pc-relative fixup range for ldr instructions (4096 bytes). Such assembler source already uses explicit .ltorg instructions to emit constant pools with regular intervals. However if we try to reuse constants emitted in earlier pools, they end up out of range. This makes the output of the testcase match what binutils gas does (prior to this patch, it would fail to assemble). Differential Revision: https://reviews.llvm.org/D32847 llvm-svn: 303540
* Re-apply r286006: Fix 24560: assembler does not share constant pool for ↵James Molloy2017-05-224-73/+58
| | | | | | | | | | | | | | | | | same constants Re-applying now that the open bug on this commit, PR32825, is known to be fixed. Original commit message: Summary: This patch returns the same label if the CP entry with the same value has been created. Reviewers: eli.friedman, rengolin, jmolloy Subscribers: majnemer, jmolloy, llvm-commits Differential Revision: https://reviews.llvm.org/D25804 llvm-svn: 303539
* Revert "[ARM] Clear the constant pool cache on explicit .ltorg directives"James Molloy2017-05-221-27/+0
| | | | | | | | This reverts commit r302416. This was a fixup for r286006, which has now been reverted so this doesn't apply (either in concept or in code). This commit itself has no problems, but the underlying issue it was fixing has now disappeared from the codebase. llvm-svn: 303536
* Revert "Fix 24560: assembler does not share constant pool for same constants"James Molloy2017-05-224-58/+73
| | | | | | This reverts commit r286006. It caused PR32825 and wasn't fixed. llvm-svn: 303535
* [AMDGPU][MC] Corrected disassembler to decode instructions with 2 literalsDmitry Preobrazhensky2017-05-191-0/+3
| | | | | | | | | | See bug 32922: https://bugs.llvm.org//show_bug.cgi?id=32922 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D32912 llvm-svn: 303428
* [AMDGPU][MC] Fixed bugs in export instructionDmitry Preobrazhensky2017-05-192-0/+52
| | | | | | | | | | | | See Bugs 33019, 33056: https://bugs.llvm.org//show_bug.cgi?id=33019 https://bugs.llvm.org//show_bug.cgi?id=33056 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33288 llvm-svn: 303423
* AMDGPU: Fix min3/max3 combines for f16/i16Matt Arsenault2017-05-171-0/+24
| | | | | | Fix missing instruction definitions for min3/max3. llvm-svn: 303284
* [Sparc] Remove execute permissions from non-executable text filesDaniel Cederman2017-05-171-0/+0
| | | | | | | | | | | | Reviewers: jyknight, lero_chris, venkatra Reviewed By: jyknight Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27127 llvm-svn: 303245
* AArch64: diagnose unrecognized features in .cpu directive.Tim Northover2017-05-151-0/+9
| | | | | | | We were silently ignoring any features we couldn't match up, which led to errors in an inline asm block missing the conventional "\n\t". llvm-svn: 303108
* [AMDGPU][MC] Corrected several VI opcodes to avoid printing _e64Dmitry Preobrazhensky2017-05-153-29/+29
| | | | | | | | | | See bug 32936: https://bugs.llvm.org//show_bug.cgi?id=32936 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D33123 llvm-svn: 303070
* [AMDGPU][MC] Removed V_MQSAD_U16_U8Dmitry Preobrazhensky2017-05-151-0/+18
| | | | | | | | | | | | This instruction does not really exist See Bug 33018: https://bugs.llvm.org//show_bug.cgi?id=33018 Reviewers: vpykhtin, artem.tamazov Differential Revision: https://reviews.llvm.org/D33126 llvm-svn: 303055
* MCObjectStreamer : fail with a diagnostic when emitting an out of range value.Arnaud A. de Grandmaison2017-05-151-0/+9
| | | | | | | | | We were previously silently emitting bogus data in release mode, making it very hard to diagnose the error, or crashing with an assert in debug mode. A proper diagnostic is now always emitted when the value to be emitted is out of range. llvm-svn: 303041
* [PPC] Change the register constraint of the first source operand of ↵Guozhi Wei2017-05-111-0/+4
| | | | | | | | | | | | instruction mtvsrdd to g8rc_nox0 According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0. This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified. Differential Revision: https://reviews.llvm.org/D32880 llvm-svn: 302834
* AMDGPU: Remove tfe bit from flat instruction definitionsMatt Arsenault2017-05-112-90/+0
| | | | | | | | | | We don't use it and it was removed in gfx9, and the encoding bit repurposed. Additionally actually using it requires changing the output register class, which wasn't done anyway. llvm-svn: 302814
* [SystemZ] Add miscellaneous instructionsUlrich Weigand2017-05-103-0/+261
| | | | | | | | This adds a few missing instructions for the assembler and disassembler. Those should be the last missing general- purpose (Chapter 7) instructions for the z10 ISA. llvm-svn: 302667
* [SystemZ] Add missing arithmetic instructionsUlrich Weigand2017-05-103-0/+1451
| | | | | | | | | This adds the remaining general arithmetic instructions for assembler / disassembler use. Most of these are not useful for codegen; a few might be, and those are listed in the README.txt for future improvements. llvm-svn: 302665
* [LLVM][inline-asm] Altmacro string escape character '!'Michael Zuckerman2017-05-101-0/+29
| | | | | | | | | | | | | This patch is the fourth patch in a series of reviews for the Altmacro feature. This patch introduces a new escape character '!' and it depends on D32701. according to https://sourceware.org/binutils/docs/as/Altmacro.html: "single-character string escape To include any single character literally in a string (even if the character would otherwise have some special meaning), you can prefix the character with !' (an exclamation mark). For example, you can write <4.3 !> 5.4!!>' to get the literal text `4.3 > 5.4!'. " Differential Revision: https://reviews.llvm.org/D32792 llvm-svn: 302652
* [AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in ↵Dmitry Preobrazhensky2017-05-104-19/+19
| | | | | | | | | | | | disassembler output See bug 32927: https://bugs.llvm.org//show_bug.cgi?id=32927 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D32913 llvm-svn: 302648
* [SystemZ] Add decimal integer instructionsUlrich Weigand2017-05-103-0/+2486
| | | | | | | This adds the set of decimal integer (BCD) instructions for assembler / disassembler use. llvm-svn: 302646
* [SystemZ] Add crypto instructionsUlrich Weigand2017-05-109-0/+296
| | | | | | | This adds the set of message-security assist instructions for assembler / disassembler use. llvm-svn: 302645
* [SystemZ] Add translate/convert instructionsUlrich Weigand2017-05-103-0/+903
| | | | | | | This adds the set of character-set translate and convert instructions for assembler / disassembler use. llvm-svn: 302644
* [SystemZ] Add missing memory/string instructionsUlrich Weigand2017-05-103-0/+452
| | | | | | | This adds a number of missing memory and string instructions for assembler / disassembler use. llvm-svn: 302643
* [SystemZ] Reformat assembler/disassembler testsUlrich Weigand2017-05-1010-6148/+6353
| | | | | | | | The assembler and disassmebler test cases started out formatted and sorted in a particular way, but this got lost over time as patches were added. Reformat them again. NFC. llvm-svn: 302642
* [ARM] Clear the constant pool cache on explicit .ltorg directivesMartin Storsjo2017-05-081-0/+27
| | | | | | | | | | | | | | | | | | | | | | Multiple ldr pseudoinstructions with the same constant value will reuse the same constant pool entry. However, if the constant pool is explicitly flushed with a .ltorg directive, we should not try to reference constants in the previous pool any longer, since they may be out of range. This fixes assembling hand-written assembler source which repeatedly loads the same constant value, across a binary size larger than the pc-relative fixup range for ldr instructions (4096 bytes). Such assembler source already uses explicit .ltorg instructions to emit constant pools with regular intervals. However if we try to reuse constants emitted in earlier pools, they end up out of range. This makes the output of the testcase match what binutils gas does (prior to this patch, it would fail to assemble). Differential Revision: https://reviews.llvm.org/D32847 llvm-svn: 302416
* [ARM] Add support for ORR and ORN instruction substitutionsJohn Brawn2017-05-053-0/+26
| | | | | | | | | | | | | Recently support was added for substituting one intruction for another by negating or inverting the immediate, but ORR and ORN were missed so this patch adds them. This one is slightly different to the others in that ORN only exists in thumb, so we only do the substitution in thumb. Differential Revision: https://reviews.llvm.org/D32534 llvm-svn: 302224
* [LLVM][inline-asm][Altmacor] Altmacro string delimiter '<..>'Michael Zuckerman2017-05-042-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | In this patch, I introduce a new altmacro string delimiter. This review is the second review in a series of four reviews. (one for each altmacro feature: LOCAL, string delimiter, string '!' escape sign and absolute expression as a string '%' ). In the alternate macro mode, you can delimit strings with matching angle brackets <..> when using it as a part of calling macro arguments. As described in the https://sourceware.org/binutils/docs-2.27/as/Altmacro.html "<string> You can delimit strings with matching angle brackets." assumptions: 1. If an argument begins with '<' and ends with '>'. The argument is considered as a string. 2. Except adding new string mark '<..>', a regular macro behavior is expected. 3. The altmacro cannot affect the regular less/greater behavior. 4. If a comma is present inside an angle brackets it considered as a character and not as a separator. Differential Revision: https://reviews.llvm.org/D32701 llvm-svn: 302135
* [AArch64] armv8-A doesn't have CRC.Ahmed Bougacha2017-05-035-61/+51
| | | | | | | | | | | That's only a required extension as of v8.1a. Remove it from the "generic" CPU as well: it should only support the base ISA (and binutils agrees). Also unify the MC tests into crc.s and arm64-crc32.s llvm-svn: 302077
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