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* [PowerPC][Altivec] Add vmr extended mnemonicNemanja Ivanovic2017-01-311-0/+3
| | | | | | | | | | | Just adds the vmr (Vector Move Register) mnemonic for the VOR instruction in the PPC back end. Committing on behalf of brunoalr (Bruno Rosa). Differential Revision: https://reviews.llvm.org/D29133 llvm-svn: 293626
* [mips] Addition of the immediate cases for the instructions [d]div, [d]divuSimon Dardis2017-01-313-121/+647
| | | | | | | | | | | | | | | | Related to http://reviews.llvm.org/D15772 Depends on http://reviews.llvm.org/D16888 Adds support for immediate operand for [D]DIV[U] instructions. Patch By: Srdjan Obucina Reviewers: zoran.jovanovic, vkalintiris, dsanders, obucina Differential Revision: https://reviews.llvm.org/D16889 llvm-svn: 293614
* Fix line endings.Eli Friedman2017-01-301-10779/+10779
| | | | llvm-svn: 293554
* Reapply [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8.Artem Tamazov2017-01-303-0/+241206
| | | | llvm-svn: 293552
* AMDGPU: Fix assembler encoding for EXP instructions on VIMarek Olsak2017-01-301-30/+58
| | | | | | | | | | Reviewers: arsenm, tstellarAMD Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28992 llvm-svn: 293476
* [X86][Disassembler] Added SALC instructionChris Ray2017-01-292-790/+797
| | | | | | | | | | | | Reviewers: joe.abbey, craig.topper Reviewed By: craig.topper Subscribers: majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D29201 llvm-svn: 293447
* Add some Book-E instructions to the asm parser and printer.Justin Hibbits2017-01-292-0/+22
| | | | | | | | | | | | | | | | | | | Summary: Adds the following instructions: * mfpmr * mtpmr * icblc * icblq * icbtls Fix the scheduling for mtspr on e5500, which uses CFX0, instead of SFX0/SFX1 as on e500mc. Addresses PR 31538. Differential Revision: https://reviews.llvm.org/D29002 llvm-svn: 293417
* [X86] Adding FFREEP instruction.Chris Ray2017-01-272-11808/+11836
| | | | | | | | | | | | | | Summary: Small change to get the FREEP instruction to decode properly. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29193 llvm-svn: 293314
* [mips] Recommit: "N64 static relocation model support"Simon Dardis2017-01-271-25/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! This version corrects a "Conditional jump or move depends on uninitialised value(s)" error detected by valgrind present in the original commit. Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293279
* Revert "[mips] N64 static relocation model support"Simon Dardis2017-01-261-91/+25
| | | | | | This reverts commit r293164. There are multiple tests failing. llvm-svn: 293170
* [mips] N64 static relocation model supportSimon Dardis2017-01-261-25/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293164
* AMDGPU: Set call_convention bit in kernel_code_tMatt Arsenault2017-01-252-2/+2
| | | | | | | According to the documentation this is supposed to be -1 if indirect calls are not supported. llvm-svn: 293081
* [X86]Enable the use of 'mov' with a 64bit GPR and a large immediateCoby Tayree2017-01-251-0/+2
| | | | | | | | | | | Enable the next form (intel style): "mov <reg64>, <largeImm>" which is should be available, where <largeImm> stands for immediates which exceed the range of a singed 32bit integer Differential Revision: https://reviews.llvm.org/D28988 llvm-svn: 293030
* Revert [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8.Ivan Krasin2017-01-243-241206/+0
| | | | | | | | | | | | Reason: broke ASAN bots with a global buffer overflow. http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/2291 Each test contains 20-30K test cases but takes only several (from 4 to 10) seconds to complete on average machine. The tests cover the majority of AMDGPU Gfx7/Gfx8 instructions, including many dark corners, and intended to quickly find out if something is broken. llvm-svn: 292974
* [CodeView] Fix off-by-one error in def range gap emissionReid Kleckner2017-01-241-0/+24
| | | | | | | | | Also fixes a much worse bug where we emitted the wrong gap size for the def range uncovered by the test for this issue. Fixes PR31726. llvm-svn: 292949
* [AMDGPU][mc][tests][NFC] Add coverage/smoke tests for Gfx7 and Gfx8.Artem Tamazov2017-01-243-0/+241206
| | | | | | | | | Each test contains 20-30K test cases but takes only several (from 4 to 10) seconds to complete on average machine. The tests cover the majority of AMDGPU Gfx7/Gfx8 instructions, including many dark corners, and intended to quickly find out if something is broken. llvm-svn: 292922
* Add LC_BUILD_VERSION load commandSteven Wu2017-01-231-0/+7
| | | | | | | | | | | | | | | | | | | Summary: Add a new load command LC_BUILD_VERSION. It is a generic version of LC_*_VERSION_MIN load_command used on Apple platforms. Instead of having a seperate load command for each platform, LC_BUILD_VERSION is recording platform info as an enum. It also records SDK version, min_os, and tools that used to build the binary. rdar://problem/29781291 Reviewers: enderby Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29044 llvm-svn: 292824
* Fix some broken CHECK lines.Benjamin Kramer2017-01-226-16/+16
| | | | | | The colon is important. llvm-svn: 292761
* [Assembler] Improve error when unable to evaluate expression.Chad Rosier2017-01-192-12/+9
| | | | | | | | | Add a SMLoc to MCExpr. Most code does not generate or consume the SMLoc (yet). Patch by Sanne Wouda <sanne.wouda@arm.com>! Differential Revision: https://reviews.llvm.org/D28861 llvm-svn: 292515
* Fix aliases to thumbfunc-based exprs to be thumbfunc.Evgeniy Stepanov2017-01-191-0/+10
| | | | | | | | | If F is a Thumb function symbol, and G = F + const, and G is a function symbol, then G is Thumb. Because what else could it be? Differential Revision: https://reviews.llvm.org/D28878 llvm-svn: 292514
* AMDGPU: Remove modifiers from v_div_scale_*Matt Arsenault2017-01-191-6/+2
| | | | | | | | They seem to produce nonsense results when used. This should be applied to the release branch. llvm-svn: 292472
* [Assembler] Fix crash when assembling .quad for AArch32.Chad Rosier2017-01-181-0/+9
| | | | | | | | | | | A 64-bit relocation does not exist in 32-bit ARMELF. Report an error instead of crashing. PR23870 Patch by Sanne Wouda (sanwou01). Differential Revision: https://reviews.llvm.org/D28851 llvm-svn: 292373
* [X86] Fix for bugzilla 31576 - add support for "data32" instruction prefixMarina Yatsina2017-01-187-0/+78
| | | | | | | | | | | This patch fixes bugzilla 31576 (https://llvm.org/bugs/show_bug.cgi?id=31576). "data32" instruction prefix was not defined in the llvm. An exception had to be added to the X86 tablegen and AsmPrinter because both "data16" and "data32" are encoded to 0x66 (but in different modes). Differential Revision: https://reviews.llvm.org/D28468 llvm-svn: 292352
* [AMDGPU] Assembler: fix v_mac_f16 immediatesSam Kolton2017-01-171-3/+16
| | | | | | | | | | Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28802 llvm-svn: 292224
* [mips] Correct c.cond.fmt instruction definition.Simon Dardis2017-01-1635-428/+643
| | | | | | | | | | | | | | | Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
* [AVX-512] Teach the disassembler about all of the EVEX gather and scatter ↵Craig Topper2017-01-161-0/+95
| | | | | | instructions. llvm-svn: 292094
* [AVX-512] Add more gather/scatter encoding test cases.Craig Topper2017-01-162-0/+176
| | | | llvm-svn: 292089
* [AVX-512] Correct memory operand size for VPGATHERQPS and VPGATHERQDCraig Topper2017-01-161-56/+56
| | | | | | | | | with ZMM index. Similar for SCATTER and the prefetch gather and scatter instructions. Fixes PR31618. llvm-svn: 292088
* [AMDGPU] Assembler: SDWA/DPP should not accept scalar registers and ↵Sam Kolton2017-01-112-1/+67
| | | | | | | | | | | | immediate operands Reviewers: artem.tamazov, nhaustov, vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28157 llvm-svn: 291668
* Drive by typo fixMatthias Braun2017-01-092-2/+2
| | | | llvm-svn: 291482
* Move test input to directory called Inputs.Daniel Jasper2017-01-063-1/+1
| | | | | | It is a common convention that our internal test runner depends upon. llvm-svn: 291227
* [PowerPC] Implement missing ISA 2.06 instructions.Tony Jiang2017-01-052-6/+44
| | | | | | | Instructions: fctidu[.], fctiwu[.], ftdiv, ftsqrt are not implemented. Implement them and add corresponding test cases in this patch. llvm-svn: 291116
* test: remove unnecessary triple argumentSaleem Abdulrasool2017-01-051-1/+1
| | | | | | | This test is entirely target agnostic. Avoid the triple to repair the build bots. llvm-svn: 291088
* MC: support passing search paths to the IASSaleem Abdulrasool2017-01-053-0/+19
| | | | | | | This is needed to support inclusion in inline assembly via the `.include` directive. llvm-svn: 291085
* [MC/COFF] Fix a test to actually check the relocation.Davide Italiano2017-01-041-1/+1
| | | | | | Inspired by r290953 + grep -R 'CHCEK'. llvm-svn: 290958
* [AMDGPU][mc] Enable absolute expressions in .hsa_code_object_isa directiveArtem Tamazov2016-12-292-16/+31
| | | | | | | | | | | Among other stuff, this allows to use predefined .option.machine_version_major /minor/stepping symbols in the directive. Relevant test expanded at once (also file renamed for clarity). Differential Revision: https://reviews.llvm.org/D28140 llvm-svn: 290710
* Attempt to make the Windows bots green after r290609.Chad Rosier2016-12-271-1/+1
| | | | llvm-svn: 290613
* [AArch64][AsmParser] Add support for parsing shift/extend operands with symbols.Chad Rosier2016-12-271-0/+42
| | | | | | Differential Revision: https://reviews.llvm.org/D27953 llvm-svn: 290609
* [AMDGPU][llvm-mc] Predefined symbols to access register counts ↵Artem Tamazov2016-12-272-0/+59
| | | | | | | | | | | | | | | | | | | | | | | (.kernel.{v|s}gpr_count) The feature allows for conditional assembly, filling the entries of .amd_kernel_code_t etc. Symbols are defined with value 0 at the beginning of each kernel scope. After each register usage, the respective symbol is set to: value = max( value, ( register index + 1 ) ) Thus, at the end of scope the value represents a count of used registers. Kernel scopes begin at .amdgpu_hsa_kernel directive, end at the next .amdgpu_hsa_kernel (or EOF, whichever comes first). There is also dummy scope that lies from the beginning of source file til the first .amdgpu_hsa_kernel. Test added. Differential Revision: https://reviews.llvm.org/D27859 llvm-svn: 290608
* [AMDGPU] Assembler: support SDWA and DPP for VOP2b instructionsSam Kolton2016-12-272-1/+48
| | | | | | | | | | Reviewers: nhaustov, artem.tamazov, vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D28051 llvm-svn: 290599
* AMDGPU: Fix missing 16-bit cmpx instructionsMatt Arsenault2016-12-221-0/+267
| | | | llvm-svn: 290349
* [AMDGPU] Disassembler: fix for disaasembling v_mac_f32/16_dpp/sdwaSam Kolton2016-12-222-3/+11
| | | | | | | | | | | | Summary: Real instruction should copy constraints from real instruction. This allows auto-generated disassembler to correctly process tied operands. Reviewers: nhaustov, vpykhtin, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D27847 llvm-svn: 290336
* [X86][AVX2] Passing the appropriate memory operand class to VPMADDWD ↵Ayman Musa2016-12-222-0/+114
| | | | | | | | | | instruction. Replacing the memory operand in the ymm version of VPMADDWD from i128mem to i256mem. Differential Revision: https://reviews.llvm.org/D28024 llvm-svn: 290333
* AMDGPU: [AMDGPU] Assembler: add .hsa_code_object_metadata directive for ↵Sam Kolton2016-12-192-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | functime metadata V2.0 Summary: Added pair of directives .hsa_code_object_metadata/.end_hsa_code_object_metadata. Between them user can put YAML string that would be directly put to the generated note. E.g.: ''' .hsa_code_object_metadata { amd.MDVersion: [ 2, 0 ] } .end_hsa_code_object_metadata ''' Based on D25046 Reviewers: vpykhtin, nhaustov, yaxunl, tstellarAMD Subscribers: arsenm, kzhuravl, wdng, nhaehnle, mgorny, tony-tye Differential Revision: https://reviews.llvm.org/D27619 llvm-svn: 290097
* [X86] [AVX512] Minor fix in encoding of scalar EVEX instructions. NFC.Michael Zuckerman2016-12-182-36/+36
| | | | | | | | | | | | Commit on behalf of Gadi Haber Removed EVEX_V512 prefix from scalar EVEX instructions since HW ignores L'L bits anyway (LIG). 4 instructions are modified. The changed encodings are validated with XED. Rviewers: delena, igorb Differential revision: https://reviews.llvm.org/D27802 llvm-svn: 290065
* AMDGPU: Fix name for v_ashrrev_i16Matt Arsenault2016-12-166-12/+12
| | | | llvm-svn: 289967
* Speculatively revert r289925, see PR31407Nico Weber2016-12-168-25/+25
| | | | llvm-svn: 289944
* Update .debug_line section version information to match DWARF version.Ekaterina Romanova2016-12-168-25/+25
| | | | | | | | | | | | One more attempt to re-commit the patch r285355, which I had to revert in r285362, because some tests were failing (the reason is because the size of the line_table varied depending on the full file name). In the past the compiler always emitted .debug_line version 2, though some opcodes from DWARF 3 (e.g. DW_LNS_set_prologue_end, DW_LNS_set_epilogue_begin or DW_LNS_set_isa) and from DWARF 4 could be emitted by the compiler. This patch changes version information of .debug_line to exactly match the DWARF version. For .debug_line version 4, a new field maximum_operations_per_instruction is emitted. Differential Revision: https://reviews.llvm.org/D16697 llvm-svn: 289925
* AMDGPU: Assembler support for vintrp instructionsMatt Arsenault2016-12-152-0/+150
| | | | llvm-svn: 289866
* Add missing triple target for numeric section flag testPrakhar Bahuguna2016-12-151-1/+1
| | | | llvm-svn: 289798
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