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* [ARM] Diagnose PC-writing instructions in IT blocksOliver Stannard2017-02-283-4/+63
| | | | | | | | | | | | In Thumb2, instructions which write to the PC are UNPREDICTABLE if they are in an IT block but not the last instruction in the block. Previously, we only diagnosed this for LDM instructions, this patch extends the diagnostic to cover all of the relevant instructions. Differential Revision: https://reviews.llvm.org/D30398 llvm-svn: 296459
* AMDGPU: Use v_med3_{f16|i16|u16}Matt Arsenault2017-02-271-0/+12
| | | | llvm-svn: 296401
* AMDGPU: Add some of the new gfx9 VOP3 instructionsMatt Arsenault2017-02-271-0/+32
| | | | llvm-svn: 296382
* AMDGPU: Add VOP3P instruction formatMatt Arsenault2017-02-274-0/+463
| | | | | | | | Add a few non-VOP3P but instructions related to packed. Includes hack with dummy operands for the benefit of the assembler llvm-svn: 296368
* [ARM] LSL #0 is an alias of MOVJohn Brawn2017-02-272-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | Currently we handle this correctly in arm, but in thumb we don't which leads to an unpredictable instruction being emitted for LSL #0 in an IT block and SP not being permitted in some cases when it should be. For the thumb2 LSL we can handle this by making LSL #0 an alias of MOV in the .td file, but for thumb1 we need to handle it in checkTargetMatchPredicate to get the IT handling right. We also need to adjust the handling of MOV rd, rn, LSL #0 to avoid generating the 16-bit encoding in an IT block. We should also adjust it to allow SP in the same way that it is allowed in MOV rd, rn, but I haven't done that here because it looks like it would take quite a lot of work to get right. Additionally correct the selection of the 16-bit shift instructions in processInstruction, where it was checking if the two registers were equal when it should have been checking if they were low. It appears that previously this code was never executed and the 16-bit encoding was selected by default, but the other changes I've done here have somehow made it start being used. Differential Revision: https://reviews.llvm.org/D30294 llvm-svn: 296342
* [AMDGPU] Runtime metadata fixes:Konstantin Zhuravlyov2017-02-275-42/+191
| | | | | | | | | | | - Verify that runtime metadata is actually valid runtime metadata when assembling, otherwise we could accept the following when assembling, but ocl runtime will reject it: .amdgpu_runtime_metadata { amd.MDVersion: [ 2, 1 ], amd.RandomUnknownKey, amd.IsaInfo: ... - Make IsaInfo optional, and always emit it. Differential Revision: https://reviews.llvm.org/D30349 llvm-svn: 296324
* Disallow redefinition of section symbols.Evgeniy Stepanov2017-02-244-140/+15
| | | | | | Differential Revision: https://reviews.llvm.org/D30235 llvm-svn: 296180
* [mips] Handle 64 bit immediate in and/or/xor pseudo instructions on mips64Simon Dardis2017-02-242-0/+521
| | | | | | | | | | | | | | | | | | | | Previously LLVM was assuming 32-bit signed immediates which results in and with a bitmask that has bit 31 set to incorrectly include bits 63-32 in the result. After applying this patch I can now compile all of the FreeBSD mips assembly code with clang. This issue also affects the nor, slt and sltu macros and I will fix those in a separate review. Patch By: Alexander Richardson Commit message reformatted by sdardis. Reviewers: atanasyan, theraven, sdardis Differential Revision: https://reviews.llvm.org/D30298 llvm-svn: 296125
* [mips][ias] Further relax operands of certain assembly instructionsSimon Dardis2017-02-231-1/+77
| | | | | | | | | | | | | | | | This patch adjusts the most relaxed predicate of immediate operands to accept immediate forms such as ~(0xf0000000|0x000f00000). Previously these forms would be accepted by GAS and rejected by IAS. This partially resolves PR/30383. Thanks to Sean Bruno for reporting the issue! Reviewers: slthakur, seanbruno Differential Revision: https://reviews.llvm.org/D29218 llvm-svn: 295965
* [WebAssembly] Implement the wasm binary container header.Dan Gohman2017-02-222-0/+11
| | | | | | | Also, update the version number to 0x1, which is what engines are now expecting. llvm-svn: 295860
* * [AMDGPU][mc][tests] Updated coverage/smoke tests for gfx7 and gfx8; minor ↵Dmitry Preobrazhensky2017-02-224-100835/+114665
| | | | | | | test corrections. NB: several old tests have been corrected because they violated constant bus limitations llvm-svn: 295834
* Test commitDmitry Preobrazhensky2017-02-212-0/+4
| | | | llvm-svn: 295740
* [ARM] Correct SP/PC handling in t2MOVrJohn Brawn2017-02-211-0/+100
| | | | | | Add a missing test that I forgot to svn add in my previous commit llvm-svn: 295734
* [mips] Add test for mul macro variantsSimon Dardis2017-02-201-0/+154
| | | | llvm-svn: 295648
* AMDGPU: Fix disassembly of aperture registersMatt Arsenault2017-02-181-0/+13
| | | | llvm-svn: 295555
* AMDGPU: Merge initial gfx9 supportMatt Arsenault2017-02-181-0/+71
| | | | llvm-svn: 295554
* [AArch64] Add Cavium ThunderX supportJoel Jones2017-02-171-0/+5175
| | | | | | | | | | | | | | This set of patches adds support for Cavium ThunderX ARM64 processors: * ThunderX * ThunderX T81 * ThunderX T83 * ThunderX T88 Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D28891 llvm-svn: 295475
* MC/COFF: Do not emit forward associative section referenceds.Rui Ueyama2017-02-171-6/+6
| | | | | | | | | | | | | | | | MSVC link.exe cannot handle associative sections that refer later sections in the section header. Technically, such COFF object doesn't violate the Microsoft COFF spec, as the spec doesn't say anything about that, but still we should avoid doing that to make it compatible with MS tools. This patch assigns smaller section numbers to non-associative sections and larger numbers to associative sections. This should resolve the compatibility issue. Differential Revision: https://reviews.llvm.org/D30080 llvm-svn: 295464
* [AArch64] AArch64AsmParser clean up of isImmediate functions. NFCSjoerd Meijer2017-02-161-7/+7
| | | | | | | | | | | Regression test neon-diagnostics.s needed changing because it now produces a more specific diagnostic about the immediate ranges. One change in the expected error message is not obvious, but there multiple candidate and it happens to pick the immediate diagnostic. Differential Revision: https://reviews.llvm.org/D29939 llvm-svn: 295331
* AMDGPU: Replace assert with report_fatal_errorMatt Arsenault2017-02-151-0/+4
| | | | | | Also use a more refined condition. llvm-svn: 295239
* [mips] Fix failing test.Simon Dardis2017-02-131-4/+4
| | | | llvm-svn: 294966
* [mips] divide macro instruction cleanup.Simon Dardis2017-02-136-113/+130
| | | | | | | | | | | | | | Clean up the implementation of divide macro expansion by getting rid of a FIXME regarding magic numbers and branch instructions. Match GAS' behaviour for expansion of ddiv / div in the two and three operand cases. Add the two operand alias for MIPSR6. Finally, optimize macro expansion cases where the divisior is the $zero register. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29887 llvm-svn: 294960
* [Hexagon] Introduce Hexagon V62Krzysztof Parzyszek2017-02-105-0/+630
| | | | llvm-svn: 294805
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-1040-1140/+1137
| | | | llvm-svn: 294753
* Make it possible to set SHF_LINK_ORDER explicitly.Rafael Espindola2017-02-095-0/+88
| | | | | | | This will make it possible to add support for gcing user metadata (asan for example). llvm-svn: 294589
* [X86] Clzero intrinsic and its addition under znver1Craig Topper2017-02-093-0/+19
| | | | | | | | | | | | | | | | | This patch does the following. 1. Adds an Intrinsic int_x86_clzero which works with __builtin_ia32_clzero 2. Identifies clzero feature using cpuid info. (Function:8000_0008, Checks if EBX[0]=1) 3. Adds the clzero feature under znver1 architecture. 4. The custom inserter is added in Lowering. 5. A testcase is added to check the intrinsic. 6. The clzero instruction is added to assembler test. Patch by Ganesh Gopalasubramanian with a couple formatting tweaks, a disassembler test, and using update_llc_test.py from me. Differential revision: https://reviews.llvm.org/D29385 llvm-svn: 294558
* Revert r294437 as it broke an asan buildbot.Amara Emerson2017-02-082-56/+56
| | | | llvm-svn: 294523
* Fix inline-asm-diags.ll on Windows, give it a triple to avoid WoA thumb ↵Reid Kleckner2017-02-081-1/+1
| | | | | | confusion llvm-svn: 294496
* Move inline asm diags tests to an ARM directory.Sanne Wouda2017-02-081-0/+9
| | | | | | | The assembler syntaxes (and parsers) differ too much to expect this test to pass for all of them. llvm-svn: 294475
* [AArch64][TableGen] Skip tied result operands for InstAliasAmara Emerson2017-02-082-56/+56
| | | | | | | | | | | | | | | | | | | | | | | This patch checks the number of operands in the resulting instruction instead of just the alias, then skips over tied operands when generating the printing method. This allows us to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARMARM. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests. Patch by Graham Hunter. Differential Revision: https://reviews.llvm.org/D29219 llvm-svn: 294437
* [X86] Remove PCOMMIT instruction support since Intel has deprecated this ↵Craig Topper2017-02-082-7/+0
| | | | | | | | instruction with no plans to release products with it. Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction llvm-svn: 294405
* [PowerPC][Altivec] Add vnot extended mnemonicNemanja Ivanovic2017-02-071-0/+3
| | | | | | | | | | Adds the vnot extended mnemonic for the vnor instruction. Committing on behalf of brunoalr (Bruno Rosa). Differential Revision: https://reviews.llvm.org/D29225 llvm-svn: 294330
* [Hexagon] Remove encoding bits from mapped instructionsKrzysztof Parzyszek2017-02-071-4/+4
| | | | | | | | | | - Map A2_zxtb to A2_andir. - Map PS_call_nr J2_call. - Map A2_tfr[t|f][new] to A2_padd[t|f][new]. Patch by Colin LeMahieu. llvm-svn: 294320
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-0612-27/+666
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
* [Hexagon] Update MCTargetDescKrzysztof Parzyszek2017-02-0613-10/+164
| | | | | | | | | | Changes include: - Updates to the instruction descriptor flags. - Improvements to the packet shuffler and checker. - Updates to the handling of certain relocations. - Better handling of duplex instructions. llvm-svn: 294226
* [mips] dla expansion without the at registerSimon Dardis2017-02-061-0/+48
| | | | | | | | | | | | | | | | | Previously only the superscalar scheduled expansion of the dla macro for MIPS64 was implemented. If assembler temporary register is not available and the optional source register is not the destination register, synthesize the address using the naive solution of adds and shifts. This partially resolves PR/30383. Thanks to Sean Bruno for reporting the issue! Reviewers: slthakur, seanbruno Differential Revision: https://reviews.llvm.org/D29328 llvm-svn: 294182
* [X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument.Craig Topper2017-02-052-6/+6
| | | | llvm-svn: 294132
* [X86] Fix printing of blendvpd/blendvps/pblendvb to include the implicit ↵Craig Topper2017-02-051-14/+14
| | | | | | %xmm0 argument. This makes codegen output more obvious about the %xmm0 usage. llvm-svn: 294131
* [AMDGPU][mc][tests][NFC] Add coverage/smoke Gfx7 asm test (3rd attempt)Artem Tamazov2017-02-031-0/+63289
| | | | llvm-svn: 294047
* [mips] Remove absolute size assertion for end directiveSimon Dardis2017-02-031-0/+22
| | | | | | | | | | | | | | The .end <symbol> directive for MIPS marks the end of a symbol and sets the symbol's size. Previously, the corresponding emitDirective handler asserted that a function's size could be evaluated to an absolute value at that point in time. This cannot be done with when directives like .align have been encountered, instead set the function's size to the corresponding symbolic expression and let ELFObjectWriter resolve the expression to an absolute value. This avoids a redundant call to evaluateAsAbsolute. llvm-svn: 294012
* Change how we handle section symbols on ELF.Rafael Espindola2017-02-024-28/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | On ELF every section can have a corresponding section symbol. When in an assembly file we have .quad .text the '.text' refers to that symbol. The way we used to handle them is to leave .text an undefined symbol until the very end when the object writer would map them to the actual section symbol. The problem with that is that anything before the end would see an undefined symbol. This could result in bad diagnostics (test/MC/AArch64/label-arithmetic-diags-elf.s), or incorrect results when using the asm streamer (est/MC/Mips/expansion-jal-sym-pic.s). Fixing this will also allow using the section symbol earlier for setting sh_link of SHF_METADATA sections. This patch includes a few hacks to avoid changing our behaviour when handling conflicts between section symbols and other symbols. I reported pr31850 to track that. llvm-svn: 293936
* [Hexagon] Adding opExtentBits and opExtentAlign to GPrel instructionsKrzysztof Parzyszek2017-02-021-4/+4
| | | | | | Patch by Colin LeMahieu. llvm-svn: 293933
* [Hexagon] Fix relocation kind for extended predicated callsKrzysztof Parzyszek2017-02-021-0/+6
| | | | | | Patch by Sid Manning. llvm-svn: 293931
* [mips] Expansion of BEQL and BNEL with immediate operandsSimon Dardis2017-02-023-1/+52
| | | | | | | | | | | | Adds support for BEQL and BNEL macros with immediate operands. Patch by: Srdjan Obucina Reviewers: dsanders, zoran.jovanovic, vkalintiris, sdardis, obucina, seanbruno Differential Revision: https://reviews.llvm.org/D17040 llvm-svn: 293905
* AMDGPU: Use source modifiers with f16->f32 conversionsMatt Arsenault2017-02-021-2/+4
| | | | | | | | | | | The operand types were defined to fit the fp16_to_fp node, which has the half as an integer type. v_cvt_f32_f16 does support source modifiers, so change this to have an FP type and modifiers. For targets without legal f16, this requires recognizing the bit operations and trying to produce them. llvm-svn: 293857
* [mips] Parse the 'bopt' and 'nobopt' directives in IAS.Simon Dardis2017-02-011-0/+16
| | | | | | | | | | | | | | | The GAS assembler supports the ".set bopt" directive but according to the sources it doesn't do anything. It's supposed to optimize branches by filling the delay slot of a branch with it's target. This patch teaches the MIPS asm parser to accept both and warn in the case of 'bopt' that the bopt directive is unsupported. This resolves PR/31841. Thanks to Sean Bruno for reporting the issue! llvm-svn: 293798
* MCMacho: Allow __thread_ptr section after dwarf sectionsMatthias Braun2017-02-011-0/+28
| | | | | | Differential Revision: https://reviews.llvm.org/D29315 llvm-svn: 293730
* MC: Introduce the ABS8 symbol modifier.Peter Collingbourne2017-01-311-0/+8
| | | | | | | | | | | @ABS8 can be applied to symbols which appear as immediate operands to instructions that have a 8-bit immediate form for that operand. It causes the assembler to use the 8-bit form and an 8-bit relocation (e.g. R_386_8 or R_X86_64_8) for the symbol. Differential Revision: https://reviews.llvm.org/D28688 llvm-svn: 293667
* [AMDGPU][mc][tests][NFC] Revert coverage/smoke Gfx7 asm testArtem Tamazov2017-01-311-63301/+0
| | | | | | | | Reason: http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/2916/testReport/junit/LLVM/MC_AMDGPU/gfx7_asm_all_s/ This seems to reveal an AMDGPU/mc issue which needs to be triaged & fixed prior re-committing the test. llvm-svn: 293642
* [ARM] Avoid using ARM instructions in Thumb modeSam Parker2017-01-311-0/+6
| | | | | | | | | | | | | | The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
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